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Date: Fri, 4 Mar 2022 18:15:53 +0800 From: <xinlei.lee@...iatek.com> To: <chunkuang.hu@...nel.org>, <p.zabel@...gutronix.de>, <airlied@...ux.ie>, <daniel@...ll.ch>, <matthias.bgg@...il.com> CC: <dri-devel@...ts.freedesktop.org>, <linux-mediatek@...ts.infradead.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <Project_Global_Chrome_Upstream_Group@...iatek.com>, <jitao.shi@...iatek.com>, <allen-kh.cheng@...iatek.com>, <rex-bc.chen@...iatek.com>, Xinlei Lee <xinlei.lee@...iatek.com> Subject: [PATCH v2,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 From: Jitao Shi <jitao.shi@...iatek.com> Old sequence: 1. Pull the MIPI signal high 2. Delay & Dsi_reset 3. Set the dsi timing register 4. dsi clk & lanes leave ulp mode and enter hs mode New sequence: 1. Set the dsi timing register 2. Pull the MIPI signal high 3. Delay & Dsi_reset 4. dsi clk & lanes leave ulp mode and enter hs mode In the new sequence 2 & 3 & 4 will be moved to dsi_enbale in later patch. Signed-off-by: Jitao Shi <jitao.shi@...iatek.com> Signed-off-by: Xinlei Lee <xinlei.lee@...iatek.com> --- drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 5d90d2eb0019..6d7b66d5da42 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi); - mtk_dsi_rxtx_control(dsi); - usleep_range(30, 100); - mtk_dsi_reset_dphy(dsi); mtk_dsi_ps_control_vact(dsi); mtk_dsi_set_vm_cmd(dsi); mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); + mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); mtk_dsi_clk_ulp_mode_leave(dsi); mtk_dsi_lane0_ulp_mode_leave(dsi); mtk_dsi_clk_hs_mode(dsi, 0); -- 2.18.0
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