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Message-Id: <20220304122424.307885-4-krzysztof.kozlowski@canonical.com>
Date: Fri, 4 Mar 2022 13:24:23 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Alim Akhtar <alim.akhtar@...sung.com>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org
Subject: [PATCH v2 3/4] arm64: dts: exynos: add a specific compatible to MCT
One compatible is used for the Multi-Core Timer on most of the Samsung
Exynos SoCs, which is correct but not specific enough. These MCT blocks
have different number of interrupts, so add a second specific
compatible to Exynos5433 and Exynos850.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Reviewed-by: Alim Akhtar <alim.akhtar@...sung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 ++-
arch/arm64/boot/dts/exynos/exynos850.dtsi | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 661567d2dd7a..017ccc2f4650 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -806,7 +806,8 @@ tmu_isp: tmu@...7c000 {
};
timer@...c0000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos5433-mct",
+ "samsung,exynos4210-mct";
reg = <0x101c0000 0x800>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index d1700e96fee2..12f7ddc6fd0a 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -181,7 +181,8 @@ chipid@...00000 {
};
timer@...40000 {
- compatible = "samsung,exynos4210-mct";
+ compatible = "samsung,exynos850-mct",
+ "samsung,exynos4210-mct";
reg = <0x10040000 0x800>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
--
2.32.0
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