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Message-ID: <198341a249ea67acbf1be00b6465aa6a4eaef6e1.1646512837.git.philipp.g.hortmann@gmail.com>
Date: Sat, 5 Mar 2022 22:32:08 +0100
From: Philipp Hortmann <philipp.g.hortmann@...il.com>
To: Forest Bond <forest@...ttletooquiet.net>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
linux-staging@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: [PATCH 2/4] staging: vt6655: Remove unused byRFType in baseband.c
Remove byRFType that support 5GHz band.
Signed-off-by: Philipp Hortmann <philipp.g.hortmann@...il.com>
---
drivers/staging/vt6655/baseband.c | 80 -------------------------------
1 file changed, 80 deletions(-)
diff --git a/drivers/staging/vt6655/baseband.c b/drivers/staging/vt6655/baseband.c
index 84fa6ea3e2e6..dfdb0ebf43b5 100644
--- a/drivers/staging/vt6655/baseband.c
+++ b/drivers/staging/vt6655/baseband.c
@@ -2065,54 +2065,6 @@ bool bb_vt3253_init(struct vnt_private *priv)
priv->dbm_threshold[1] = -50;
priv->dbm_threshold[2] = 0;
priv->dbm_threshold[3] = 0;
- } else if (by_rf_type == RF_UW2452) {
- for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
- result &= bb_write_embedded(priv,
- byVT3253B0_UW2451[ii][0],
- byVT3253B0_UW2451[ii][1]);
-
- /* Init ANT B select,
- * TX Config CR09 = 0x61->0x45,
- * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
- */
-
- /*bResult &= bb_write_embedded(iobase,0x09,0x41);*/
-
- /* Init ANT B select,
- * RX Config CR10 = 0x28->0x2A,
- * 0x2A->0x28(VC1/VC2 define,
- * make the ANT_A, ANT_B inverted)
- */
-
- /*bResult &= bb_write_embedded(iobase,0x0a,0x28);*/
- /* Select VC1/VC2, CR215 = 0x02->0x06 */
- result &= bb_write_embedded(priv, 0xd7, 0x06);
-
- /* {{RobertYu:20050125, request by Jack */
- result &= bb_write_embedded(priv, 0x90, 0x20);
- result &= bb_write_embedded(priv, 0x97, 0xeb);
- /* }} */
-
- /* {{RobertYu:20050221, request by Jack */
- result &= bb_write_embedded(priv, 0xa6, 0x00);
- result &= bb_write_embedded(priv, 0xa8, 0x30);
- /* }} */
- result &= bb_write_embedded(priv, 0xb0, 0x58);
-
- for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
- result &= bb_write_embedded(priv,
- byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
-
- priv->abyBBVGA[0] = 0x14;
- priv->abyBBVGA[1] = 0x0A;
- priv->abyBBVGA[2] = 0x0;
- priv->abyBBVGA[3] = 0x0;
- priv->dbm_threshold[0] = -60;
- priv->dbm_threshold[1] = -50;
- priv->dbm_threshold[2] = 0;
- priv->dbm_threshold[3] = 0;
- /* }} RobertYu */
-
} else if (by_rf_type == RF_VT3226) {
for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
result &= bb_write_embedded(priv,
@@ -2134,38 +2086,6 @@ bool bb_vt3253_init(struct vnt_private *priv)
/* Fix VT3226 DFC system timing issue */
MACvSetRFLE_LatchBase(iobase);
/* {{ RobertYu: 20050104 */
- } else if (by_rf_type == RF_AIROHA7230) {
- for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
- result &= bb_write_embedded(priv,
- byVT3253B0_AIROHA2230[ii][0],
- byVT3253B0_AIROHA2230[ii][1]);
-
- /* {{ RobertYu:20050223, request by JerryChung */
- /* Init ANT B select,TX Config CR09 = 0x61->0x45,
- * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
- */
- /* bResult &= bb_write_embedded(iobase,0x09,0x41);*/
- /* Init ANT B select,RX Config CR10 = 0x28->0x2A,
- * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
- */
- /* bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
- /* Select VC1/VC2, CR215 = 0x02->0x06 */
- result &= bb_write_embedded(priv, 0xd7, 0x06);
- /* }} */
-
- for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
- result &= bb_write_embedded(priv,
- byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
-
- priv->abyBBVGA[0] = 0x1C;
- priv->abyBBVGA[1] = 0x10;
- priv->abyBBVGA[2] = 0x0;
- priv->abyBBVGA[3] = 0x0;
- priv->dbm_threshold[0] = -70;
- priv->dbm_threshold[1] = -48;
- priv->dbm_threshold[2] = 0;
- priv->dbm_threshold[3] = 0;
- /* }} RobertYu */
} else {
/* No VGA Table now */
priv->bUpdateBBVGA = false;
--
2.25.1
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