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Message-Id: <20220306111125.116455-10-krzysztof.kozlowski@canonical.com>
Date: Sun, 6 Mar 2022 12:11:22 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To: Alim Akhtar <alim.akhtar@...sung.com>,
Avri Altman <avri.altman@....com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Wei Xu <xuwei5@...ilicon.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Jan Kotas <jank@...ence.com>, Li Wei <liwei213@...wei.com>,
Stanley Chu <stanley.chu@...iatek.com>,
Vignesh Raghavendra <vigneshr@...com>,
linux-scsi@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org,
linux-mediatek@...ts.infradead.org
Subject: [PATCH v3 09/12] arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS
The DT schema expects 'freq-table-hz' property to be an uint32-matrix,
which is also easier to read.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 ++--
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 8bd6d7e8a474..6b3057a09251 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -1045,8 +1045,8 @@ ufs: ufs@...b0000 {
clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
clock-names = "ref_clk", "phy_clk";
- freq-table-hz = <0 0
- 0 0>;
+ freq-table-hz = <0 0>,
+ <0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 636c8817df7e..3125c3869c69 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -671,8 +671,8 @@ ufs: ufs@...c0000 {
clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
clock-names = "ref_clk", "phy_clk";
- freq-table-hz = <0 0
- 0 0>;
+ freq-table-hz = <0 0>,
+ <0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";
--
2.32.0
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