linux-kernel - Re: [PATCH V3 1/7] spi: mediatek: support tick_delay without enhance

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Date:   Mon, 7 Mar 2022 11:28:50 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...labora.com>
To:     Leilk Liu <leilk.liu@...iatek.com>, Mark Brown <broonie@...nel.org>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-spi@...r.kernel.org,
        linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH V3 1/7] spi: mediatek: support tick_delay without
 enhance_timing

Il 07/03/22 07:52, Leilk Liu ha scritto:
> this patch support tick_delay bit[31:30] without enhance_timing feature.
> 
> Fixes: f84d866ab43f("spi: mediatek: add tick_delay support")
> Signed-off-by: Leilk Liu <leilk.liu@...iatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

> ---
>   drivers/spi/spi-mt65xx.c | 15 ++++++++++++---
>   1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
> index bbfeb8046c17..3fd89548ec3c 100644
> --- a/drivers/spi/spi-mt65xx.c
> +++ b/drivers/spi/spi-mt65xx.c
> @@ -43,8 +43,11 @@
>   #define SPI_CFG1_PACKET_LOOP_OFFSET       8
>   #define SPI_CFG1_PACKET_LENGTH_OFFSET     16
>   #define SPI_CFG1_GET_TICK_DLY_OFFSET      29
> +#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1   30
>   
>   #define SPI_CFG1_GET_TICK_DLY_MASK        0xe0000000
> +#define SPI_CFG1_GET_TICK_DLY_MASK_V1     0xc0000000
> +
>   #define SPI_CFG1_CS_IDLE_MASK             0xff
>   #define SPI_CFG1_PACKET_LOOP_MASK         0xff00
>   #define SPI_CFG1_PACKET_LENGTH_MASK       0x3ff0000
> @@ -346,9 +349,15 @@ static int mtk_spi_prepare_message(struct spi_master *master,
>   
>   	/* tick delay */
>   	reg_val = readl(mdata->base + SPI_CFG1_REG);
> -	reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
> -	reg_val |= ((chip_config->tick_delay & 0x7)
> -		<< SPI_CFG1_GET_TICK_DLY_OFFSET);
> +	if (mdata->dev_comp->enhance_timing) {
> +		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
> +		reg_val |= ((chip_config->tick_delay & 0x7)
> +			    << SPI_CFG1_GET_TICK_DLY_OFFSET);
> +	} else {
> +		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
> +		reg_val |= ((chip_config->tick_delay & 0x3)
> +			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
> +	}
>   	writel(reg_val, mdata->base + SPI_CFG1_REG);
>   
>   	/* set hw cs timing */