[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <164668950224.3277206.2552145973830842260.b4-ty@kernel.org>
Date: Mon, 7 Mar 2022 22:03:32 +0000
From: Will Deacon <will@...nel.org>
To: catalin.marinas@....com, Linu Cherian <lcherian@...vell.com>,
maz@...nel.org, tglx@...utronix.de
Cc: kernel-team@...roid.com, Will Deacon <will@...nel.org>,
linuc.decode@...il.com, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH V3] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
On Mon, 7 Mar 2022 20:00:14 +0530, Linu Cherian wrote:
> When a IAR register read races with a GIC interrupt RELEASE event,
> GIC-CPU interface could wrongly return a valid INTID to the CPU
> for an interrupt that is already released(non activated) instead of 0x3ff.
>
> As a side effect, an interrupt handler could run twice, once with
> interrupt priority and then with idle priority.
>
> [...]
Applied to arm64 (for-next/errata), thanks!
[1/1] irqchip/gic-v3: Workaround Marvell erratum 38545 when reading IAR
https://git.kernel.org/arm64/c/24a147bcef8c
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
Powered by blists - more mailing lists