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Message-Id: <164668935493.3276132.12110588269320094587.b4-ty@kernel.org>
Date: Mon, 7 Mar 2022 22:03:36 +0000
From: Will Deacon <will@...nel.org>
To: mike.kravetz@...cle.com, osalvador@...e.de, rientjes@...gle.com,
mark.rutland@....com, Muchun Song <songmuchun@...edance.com>,
akpm@...ux-foundation.org, james.morse@....com,
bodeddub@...zon.com, david@...hat.com, catalin.marinas@....com,
song.bao.hua@...ilicon.com
Cc: kernel-team@...roid.com, Will Deacon <will@...nel.org>,
smuchun@...il.com, linux-kernel@...r.kernel.org,
duanxiongchun@...edance.com, linux-mm@...ck.org,
linux-arm-kernel@...ts.infradead.org, fam.zheng@...edance.com
Subject: Re: [PATCH v2 RESEND 1/2] arm64: avoid flushing icache multiple times on contiguous HugeTLB
On Wed, 2 Mar 2022 16:46:23 +0800, Muchun Song wrote:
> When a contiguous HugeTLB page is mapped, set_pte_at() will be called
> CONT_PTES/CONT_PMDS times. Therefore, __sync_icache_dcache() will
> flush cache multiple times if the page is executable (to ensure
> the I-D cache coherency). However, the first flushing cache already
> covers subsequent cache flush operations. So only flusing cache
> for the head page if it is a HugeTLB page to avoid redundant cache
> flushing. In the next patch, it is also depends on this change
> since the tail vmemmap pages of HugeTLB is mapped with read-only
> meanning only head page struct can be modified.
>
> [...]
Applied first patch only to arm64 (for-next/mm), thanks!
[1/2] arm64: avoid flushing icache multiple times on contiguous HugeTLB
https://git.kernel.org/arm64/c/cf5a501d985b
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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