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Message-Id: <20220307160918.v3.4.I01c6a2b2db578136686b42d463af985cfdff2fd9@changeid>
Date: Mon, 7 Mar 2022 16:09:34 -0800
From: Brian Norris <briannorris@...omium.org>
To: MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Rob Herring <robh+dt@...nel.org>
Cc: Lin Huang <hl@...k-chips.com>, Heiko Stuebner <heiko@...ech.de>,
Derek Basehore <dbasehore@...omium.org>,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Brian Norris <briannorris@...omium.org>,
Rob Herring <robh@...nel.org>
Subject: [PATCH v3 04/15] dt-bindings: devfreq: rk3399_dmc: Specify idle params in nanoseconds
It's inefficient to use the same number of cycles for all OPPs, since
lower frequencies make for longer idle times. Let's specify the idle
time instead, so software can pick the optimal number of cycles on its
own.
NB: these bindings aren't used anywhere yet.
Signed-off-by: Brian Norris <briannorris@...omium.org>
Reviewed-by: Rob Herring <robh@...nel.org>
---
Changes in v3:
* Add Reviewed-by
Changes in v2:
* New patch
.../bindings/devfreq/rk3399_dmc.yaml | 50 +++++++++++++++++--
1 file changed, 45 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
index 2904ae4115f3..6a33a7b44741 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.yaml
@@ -56,42 +56,52 @@ properties:
being used.
rockchip,pd_idle:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Configure the PD_IDLE value. Defines the power-down idle period in which
memories are placed into power-down mode if bus is idle for PD_IDLE DFI
clock cycles.
+ See also rockchip,pd-idle-ns.
rockchip,sr_idle:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Configure the SR_IDLE value. Defines the self-refresh idle period in
which memories are placed into self-refresh mode if bus is idle for
SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
Default value is "0".
+ See also rockchip,sr-idle-ns.
rockchip,sr_mc_gate_idle:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the memory self-refresh and controller clock gating idle period.
Memories are placed into self-refresh mode and memory controller clock
arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
cycles.
+ See also rockchip,sr-mc-gate-idle-ns.
rockchip,srpd_lite_idle:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the self-refresh power down idle period in which memories are
placed into self-refresh power down mode if bus is idle for
srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
only.
+ See also rockchip,srpd-lite-idle-ns.
rockchip,standby_idle:
+ deprecated: true
$ref: /schemas/types.yaml#/definitions/uint32
description:
Defines the standby idle period in which memories are placed into
self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
if bus is idle for standby_idle * DFI clock cycles.
+ See also rockchip,standby-idle-ns.
rockchip,dram_dll_dis_freq:
deprecated: true
@@ -260,6 +270,36 @@ properties:
When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
strength. Default value is 60.
+ rockchip,pd-idle-ns:
+ description:
+ Configure the PD_IDLE value in nanoseconds. Defines the power-down idle
+ period in which memories are placed into power-down mode if bus is idle
+ for PD_IDLE nanoseconds.
+
+ rockchip,sr-idle-ns:
+ description:
+ Configure the SR_IDLE value in nanoseconds. Defines the self-refresh idle
+ period in which memories are placed into self-refresh mode if bus is idle
+ for SR_IDLE nanoseconds. Default value is "0".
+
+ rockchip,sr-mc-gate-idle-ns:
+ description:
+ Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
+ Memories are placed into self-refresh mode and memory controller clock
+ arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
+
+ rockchip,srpd-lite-idle-ns:
+ description:
+ Defines the self-refresh power down idle period in which memories are
+ placed into self-refresh power down mode if bus is idle for
+ srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
+
+ rockchip,standby-idle-ns:
+ description:
+ Defines the standby idle period in which memories are placed into
+ self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
+ if bus is idle for standby_idle nanoseconds.
+
required:
- compatible
- devfreq-events
@@ -283,11 +323,11 @@ examples:
clock-names = "dmc_clk";
operating-points-v2 = <&dmc_opp_table>;
center-supply = <&ppvar_centerlogic>;
- rockchip,pd_idle = <0x40>;
- rockchip,sr_idle = <0x2>;
- rockchip,sr_mc_gate_idle = <0x3>;
- rockchip,srpd_lite_idle = <0x4>;
- rockchip,standby_idle = <0x2000>;
+ rockchip,pd-idle-ns = <160>;
+ rockchip,sr-idle-ns = <10240>;
+ rockchip,sr-mc-gate-idle-ns = <40960>;
+ rockchip,srpd-lite-idle-ns = <61440>;
+ rockchip,standby-idle-ns = <81920>;
rockchip,ddr3_odt_dis_freq = <333000000>;
rockchip,lpddr3_odt_dis_freq = <333000000>;
rockchip,lpddr4_odt_dis_freq = <333000000>;
--
2.35.1.616.g0bdcbb4464-goog
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