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Message-Id: <20220308110825.v4.8.I0f36da588afd01d0dc9ce5866240efa34bd91e21@changeid>
Date: Tue, 8 Mar 2022 11:08:54 -0800
From: Brian Norris <briannorris@...omium.org>
To: MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Rob Herring <robh+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>
Cc: Derek Basehore <dbasehore@...omium.org>,
devicetree@...r.kernel.org, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org, Lin Huang <hl@...k-chips.com>,
linux-arm-kernel@...ts.infradead.org, linux-pm@...r.kernel.org,
Brian Norris <briannorris@...omium.org>
Subject: [PATCH v4 08/15] PM / devfreq: rk3399_dmc: Use bitfield macro definitions for ODT_PD
We're going to add new usages, and it's cleaner to work with macros
instead of comments and magic numbers.
Signed-off-by: Brian Norris <briannorris@...omium.org>
---
(no changes since v1)
drivers/devfreq/rk3399_dmc.c | 43 ++++++++++++++++++++----------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
index 8f447217303f..c4efbc15cbb1 100644
--- a/drivers/devfreq/rk3399_dmc.c
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -5,6 +5,7 @@
*/
#include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/devfreq.h>
@@ -23,6 +24,15 @@
#include <soc/rockchip/rk3399_grf.h>
#include <soc/rockchip/rockchip_sip.h>
+#define RK3399_SET_ODT_PD_0_SR_IDLE GENMASK(7, 0)
+#define RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE GENMASK(15, 8)
+#define RK3399_SET_ODT_PD_0_STANDBY_IDLE GENMASK(31, 16)
+
+#define RK3399_SET_ODT_PD_1_PD_IDLE GENMASK(11, 0)
+#define RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE GENMASK(27, 16)
+
+#define RK3399_SET_ODT_PD_2_ODT_ENABLE BIT(0)
+
struct rk3399_dmcfreq {
struct device *dev;
struct devfreq *devfreq;
@@ -55,7 +65,6 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
unsigned long old_clk_rate = dmcfreq->rate;
unsigned long target_volt, target_rate;
struct arm_smccc_res res;
- bool odt_enable = false;
int err;
opp = devfreq_recommended_opp(dev, freq, flags);
@@ -72,8 +81,10 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
mutex_lock(&dmcfreq->lock);
if (dmcfreq->regmap_pmu) {
+ unsigned int odt_pd_arg2 = 0;
+
if (target_rate >= dmcfreq->odt_dis_freq)
- odt_enable = true;
+ odt_pd_arg2 |= RK3399_SET_ODT_PD_2_ODT_ENABLE;
/*
* This makes a SMC call to the TF-A to set the DDR PD
@@ -83,7 +94,7 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0,
dmcfreq->odt_pd_arg1,
ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD,
- odt_enable, 0, 0, 0, &res);
+ odt_pd_arg2, 0, 0, 0, &res);
}
/*
@@ -316,23 +327,17 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev)
/*
* In TF-A there is a platform SIP call to set the PD (power-down)
* timings and to enable or disable the ODT (on-die termination).
- * This call needs three arguments as follows:
- *
- * arg0:
- * bit[0-7] : sr_idle
- * bit[8-15] : sr_mc_gate_idle
- * bit[16-31] : standby idle
- * arg1:
- * bit[0-11] : pd_idle
- * bit[16-27] : srpd_lite_idle
- * arg2:
- * bit[0] : odt enable
*/
- data->odt_pd_arg0 = (data->sr_idle & 0xff) |
- ((data->sr_mc_gate_idle & 0xff) << 8) |
- ((data->standby_idle & 0xffff) << 16);
- data->odt_pd_arg1 = (data->pd_idle & 0xfff) |
- ((data->srpd_lite_idle & 0xfff) << 16);
+ data->odt_pd_arg0 =
+ FIELD_PREP(RK3399_SET_ODT_PD_0_SR_IDLE, data->sr_idle) |
+ FIELD_PREP(RK3399_SET_ODT_PD_0_SR_MC_GATE_IDLE,
+ data->sr_mc_gate_idle) |
+ FIELD_PREP(RK3399_SET_ODT_PD_0_STANDBY_IDLE,
+ data->standby_idle);
+ data->odt_pd_arg1 =
+ FIELD_PREP(RK3399_SET_ODT_PD_1_PD_IDLE, data->pd_idle) |
+ FIELD_PREP(RK3399_SET_ODT_PD_1_SRPD_LITE_IDLE,
+ data->srpd_lite_idle);
/*
* We add a devfreq driver to our parent since it has a device tree node
--
2.35.1.616.g0bdcbb4464-goog
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