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Message-Id: <20220308010537.70150-1-mike.travis@hpe.com>
Date: Mon, 7 Mar 2022 19:05:33 -0600
From: Mike Travis <mike.travis@....com>
To: Borislav Petkov <bp@...en8.de>, Ingo Molnar <mingo@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
Steve Wahl <steve.wahl@....com>, x86@...nel.org
Cc: Mike Travis <mike.travis@....com>,
Andy Shevchenko <andy@...radead.org>,
Darren Hart <dvhart@...radead.org>,
Dimitri Sivanich <dimitri.sivanich@....com>,
"H. Peter Anvin" <hpa@...or.com>,
Russ Anderson <russ.anderson@....com>,
linux-kernel@...r.kernel.org, platform-driver-x86@...r.kernel.org
Subject: [PATCH 0/4] x86/platform/uv: UV Kernel support for UV5
Remove obsolete scratch5 NMI handler
Removes obsolete scratch5 NMI handler only used in UV1 and early UV2
systems.
Update NMI setup for UV5
Update NMI handler to interface with UV5 hardware. This involves
changing the EVENT_OCCURRED MMR used by the hardware and removes
the check for the newer NMI function supported by UV BIOS.
Update TSC sync check for UV5
Update TSC to not check TSC sync state for uv5+ as it is not
available. Therefore it is assumed that TSC will always be in
sync for multiple chassis and will pass the tests for the kernel
to accept it as the clocksource. To disable this check use the
kernel start options tsc=reliable clocksource=tsc.
Add gap hole end size
Show value of gap end in kernel log which equates to number of
physical address bits used by system. The structure stores PA
bits 56:26, for 64MB granularity, up to 64PB max size.
Mike Travis (4):
x86/platform/uv: Remove Obsolete Scratch5 NMI handler
x86/platform/uv: Update NMI Handler for UV5
x86/platform/uv: Update TSC sync state for UV5
x86/platform/uv: Add gap hole end size
arch/x86/include/asm/uv/uv_hub.h | 6 ------
arch/x86/kernel/apic/x2apic_uv_x.c | 20 +++++++++++++++-----
arch/x86/platform/uv/uv_nmi.c | 27 ++++++++++++---------------
3 files changed, 27 insertions(+), 26 deletions(-)
--
2.26.2
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