linux-kernel - [PATCH v2 2/4] dt-bindings: timer: exynos4210-mct: Support using only local timer

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 8 Mar 2022 15:24:08 +0100
From:   Vincent Whitchurch <vincent.whitchurch@...s.com>
To:     <krzysztof.kozlowski@...onical.com>, <tglx@...utronix.de>,
        <daniel.lezcano@...aro.org>
CC:     <kernel@...s.com>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-samsung-soc@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <alim.akhtar@...sung.com>, <robh+dt@...nel.org>,
        Vincent Whitchurch <vincent.whitchurch@...s.com>
Subject: [PATCH v2 2/4] dt-bindings: timer: exynos4210-mct: Support using only local timer

The ARTPEC-8 SoC has a quad-core Cortex-A53 and a single-core Cortex-A5
which share one MCT with one global and eight local timers.  The
Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and
therefore run two separate kernels.

The Cortex-A53 boots first and starts the global FRC and also registers
a clock events device using the global timer.  (This global timer clock
events is usually replaced by arch timer clock events for each of the
cores.)

When the A5 boots, we should not use the global timer interrupts or
write to the global timer registers.  This is because even if there are
four global comparators, the control bits for all four are in the same
registers, and we would need to synchronize between the cpus.  Instead,
the global timer FRC (already started by the A53) should be used as the
clock source, and one of the local timers which are not used by the A53
can be used for clock events on the A5.

To support this usecase, add a property to the binding to specify the
first local timer index to be used. If this parameter is non-zero, the
global timer interrupts will also not be used.

Signed-off-by: Vincent Whitchurch <vincent.whitchurch@...s.com>
---

Notes:
    v2: New.

 .../bindings/timer/samsung,exynos4210-mct.yaml           | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
index dce42f1f7574..46f466081836 100644
--- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
+++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
@@ -47,6 +47,15 @@ properties:
   reg:
     maxItems: 1

+  local-timer-index:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 0
+    maximum: 15     # Last local timer index
+    description: |
+      If present, sets the first local timer index to use.  If this value is
+      set to a non-default value, the global timer will not be used for
+      interrupts.
+
   interrupts:
     description: |
       Interrupts should be put in specific order. This is, the local timer
-- 
2.34.1