linux-kernel - [PATCH] perf/x86: cleanup comments

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Date:   Mon,  7 Mar 2022 17:51:48 -0800
From:   trix@...hat.com
To:     peterz@...radead.org, mingo@...hat.com, acme@...nel.org,
        mark.rutland@....com, alexander.shishkin@...ux.intel.com,
        jolsa@...nel.org, namhyung@...nel.org, tglx@...utronix.de,
        bp@...en8.de, dave.hansen@...ux.intel.com, hpa@...or.com
Cc:     x86@...nel.org, linux-perf-users@...r.kernel.org,
        linux-kernel@...r.kernel.org, Tom Rix <trix@...hat.com>
Subject: [PATCH] perf/x86: cleanup comments

From: Tom Rix <trix@...hat.com>

For spdx, // for *.c

Replacements
certan to certain
fecthes to fetches
funning to running
dont to don't

Signed-off-by: Tom Rix <trix@...hat.com>
---
 arch/x86/events/amd/core.c               | 2 +-
 arch/x86/events/core.c                   | 2 +-
 arch/x86/events/intel/p4.c               | 2 +-
 arch/x86/events/intel/uncore.c           | 2 +-
 arch/x86/events/intel/uncore_discovery.c | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 9687a8aef01c5..aec3a6134f745 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -81,7 +81,7 @@ static __initconst const u64 amd_hw_cache_event_ids
  },
  [ C(ITLB) ] = {
 	[ C(OP_READ) ] = {
-		[ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
+		[ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fetches        */
 		[ C(RESULT_MISS)   ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
 	},
 	[ C(OP_WRITE) ] = {
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index eef816fc216d3..0b05317d3fc91 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1416,7 +1416,7 @@ int x86_perf_event_set_period(struct perf_event *event)
 		wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff);
 
 	/*
-	 * Due to erratum on certan cpu we need
+	 * Due to erratum on certain cpu we need
 	 * a second write to be sure the register
 	 * is updated properly
 	 */
diff --git a/arch/x86/events/intel/p4.c b/arch/x86/events/intel/p4.c
index 7951a5dc73b63..e21c7e1684933 100644
--- a/arch/x86/events/intel/p4.c
+++ b/arch/x86/events/intel/p4.c
@@ -960,7 +960,7 @@ static void __p4_pmu_enable_event(struct perf_event *event)
 	escr_addr = bind->escr_msr[thread];
 
 	/*
-	 * - we dont support cascaded counters yet
+	 * - we don't support cascaded counters yet
 	 * - and counter 1 is broken (erratum)
 	 */
 	WARN_ON_ONCE(p4_is_event_cascaded(hwc->config));
diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c
index e497da9bf4270..79bfc87f2939e 100644
--- a/arch/x86/events/intel/uncore.c
+++ b/arch/x86/events/intel/uncore.c
@@ -573,7 +573,7 @@ int uncore_pmu_event_add(struct perf_event *event, int flags)
 		return -ENODEV;
 
 	/*
-	 * The free funning counter is assigned in event_init().
+	 * The free running counter is assigned in event_init().
 	 * The free running counter event and free running counter
 	 * are 1:1 mapped. It doesn't need to be tracked in event_list.
 	 */
diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/intel/uncore_discovery.c
index 5fd72d4b8bbb0..955d5a48554da 100644
--- a/arch/x86/events/intel/uncore_discovery.c
+++ b/arch/x86/events/intel/uncore_discovery.c
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Support Intel uncore PerfMon discovery mechanism.
  * Copyright(c) 2021 Intel Corporation.
-- 
2.26.3