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Message-ID: <6c03c8f1-2267-6e1e-71ff-8609f16ca7c5@collabora.com>
Date: Wed, 9 Mar 2022 09:39:02 -0300
From: Ariel D'Alessandro <ariel.dalessandro@...labora.com>
To: Shawn Guo <shawnguo@...nel.org>
Cc: alsa-devel@...a-project.org, devicetree@...r.kernel.org,
kernel@...gutronix.de, linux-arm-kernel@...ts.infradead.org,
linux-imx@....com, linux-kernel@...r.kernel.org,
broonie@...nel.org, festevam@...il.com,
krzysztof.kozlowski@...onical.com, lgirdwood@...il.com,
michael@...rulasolutions.com, robh+dt@...nel.org,
s.hauer@...gutronix.de
Subject: Re: [PATCH v3] arm64: dts: imx8mn-bsh-smm-s2pro: Add tlv320aic31xx
audio card node
Hi,
Can we get this integrated into the linux-next tree so it's available
for the next merge window?
Regards,
Ariel
On 2/21/22 01:00, Shawn Guo wrote:
> On Mon, Feb 14, 2022 at 09:03:07AM -0300, Ariel D'Alessandro wrote:
>> BSH SystemMaster (SMM) S2 PRO board comes with an audio card based on
>> tlv320aic31xx family codec.
>>
>> The audio card exposes two playback devices, one of them using the EASRC
>> (Enhanced Asynchronous Sample Rate Converter) module. Note that this
>> would require SDMA and EASRC firmware in order to work.
>>
>> Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@...labora.com>
>> Signed-off-by: Michael Trimarchi <michael@...rulasolutions.com>
>> ---
>> .../dts/freescale/imx8mn-bsh-smm-s2pro.dts | 94 +++++++++++++++++++
>> 1 file changed, 94 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts
>> index c6a8ed6745c1..44e2635d3096 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts
>> @@ -7,6 +7,7 @@
>> /dts-v1/;
>>
>> #include "imx8mn-bsh-smm-s2-common.dtsi"
>> +#include <dt-bindings/sound/tlv320aic31xx.h>
>
> Ping me when this header lands on Linus's tree.
>
> Shawn
>
>>
>> / {
>> model = "BSH SMM S2 PRO";
>> @@ -16,6 +17,69 @@ memory@...00000 {
>> device_type = "memory";
>> reg = <0x0 0x40000000 0x0 0x20000000>;
>> };
>> +
>> + sound-tlv320aic31xx {
>> + compatible = "fsl,imx-audio-tlv320aic31xx";
>> + model = "tlv320aic31xx-hifi";
>> + audio-cpu = <&sai3>;
>> + audio-codec = <&codec>;
>> + audio-asrc = <&easrc>;
>> + audio-routing =
>> + "Ext Spk", "SPL",
>> + "Ext Spk", "SPR";
>> + mclk-id = <PLL_CLKIN_BCLK>;
>> + };
>> +
>> + vdd_input: vdd_input {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vdd_input";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + };
>> +};
>> +
>> +&easrc {
>> + fsl,asrc-rate = <48000>;
>> + fsl,asrc-format = <10>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <400000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c2>;
>> + status = "okay";
>> +
>> + tlv320dac3101: audio-codec@18 {
>> + #sound-dai-cells = <0>;
>> + compatible = "ti,tlv320dac3101";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_dac_rst>;
>> + reg = <0x18>;
>> +
>> + ai31xx-micbias-vg = <MICBIAS_AVDDV>;
>> +
>> + HPVDD-supply = <&buck4_reg>;
>> + SPRVDD-supply = <&vdd_input>;
>> + SPLVDD-supply = <&vdd_input>;
>> + AVDD-supply = <&buck4_reg>;
>> + IOVDD-supply = <&buck4_reg>;
>> + DVDD-supply = <&buck5_reg>;
>> + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
>> +
>> + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
>> + clock-names = "mclk";
>> + };
>> +};
>> +
>> +&sai3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_sai3>;
>> + assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
>> + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
>> + assigned-clock-rates = <24576000>;
>> + fsl,sai-mclk-direction-output;
>> + status = "okay";
>> };
>>
>> /* eMMC */
>> @@ -30,6 +94,36 @@ &usdhc1 {
>> };
>>
>> &iomuxc {
>> + pinctrl_dac_rst: dacrstgrp {
>> + fsl,pins = <
>> + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */
>> + >;
>> + };
>> +
>> + pinctrl_espi2: espi2grp {
>> + fsl,pins = <
>> + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
>> + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
>> + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
>> + MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2c2grp {
>> + fsl,pins = <
>> + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
>> + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
>> + >;
>> + };
>> +
>> + pinctrl_sai3: sai3grp {
>> + fsl,pins = <
>> + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
>> + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
>> + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
>> + >;
>> + };
>> +
>> pinctrl_usdhc1: usdhc1grp {
>> fsl,pins = <
>> MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
>> --
>> 2.34.1
>>
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