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Message-ID: <mhng-3d749a55-0e5d-49fd-8682-06e8a058dfe0@palmer-ri-x1c9>
Date: Thu, 10 Mar 2022 12:07:02 -0800 (PST)
From: Palmer Dabbelt <palmer@...belt.com>
To: jszhang@...nel.org
CC: Paul Walmsley <paul.walmsley@...ive.com>, aou@...s.berkeley.edu,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
heiko@...ech.de
Subject: Re: [PATCH] riscv: alternative only works on !XIP_KERNEL
On Thu, 10 Feb 2022 08:49:43 PST (-0800), jszhang@...nel.org wrote:
> The alternative mechanism needs runtime code patching, it can't work
> on XIP_KERNEL. And the errata workarounds are implemented via the
> alternative mechanism. So add !XIP_KERNEL dependency for alternative
> and erratas.
>
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> ---
> arch/riscv/Kconfig.erratas | 1 +
> arch/riscv/Kconfig.socs | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
> index b44d6ecdb46e..0aacd7052585 100644
> --- a/arch/riscv/Kconfig.erratas
> +++ b/arch/riscv/Kconfig.erratas
> @@ -2,6 +2,7 @@ menu "CPU errata selection"
>
> config RISCV_ERRATA_ALTERNATIVE
> bool "RISC-V alternative scheme"
> + depends on !XIP_KERNEL
> default y
> help
> This Kconfig allows the kernel to automatically patch the
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 6ec44a22278a..c112ab2a9052 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -14,8 +14,8 @@ config SOC_SIFIVE
> select CLK_SIFIVE
> select CLK_SIFIVE_PRCI
> select SIFIVE_PLIC
> - select RISCV_ERRATA_ALTERNATIVE
> - select ERRATA_SIFIVE
> + select RISCV_ERRATA_ALTERNATIVE if !XIP_KERNEL
> + select ERRATA_SIFIVE if !XIP_KERNEL
> help
> This enables support for SiFive SoC platform hardware.
Thanks, this is on fixes.
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