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Message-ID: <YipjOXdCNUxdy+ey@robh.at.kernel.org>
Date: Thu, 10 Mar 2022 14:44:41 -0600
From: Rob Herring <robh@...nel.org>
To: Tim Chang <jia-wei.chang@...iatek.com>
Cc: "Rafael J . Wysocki" <rafael@...nel.org>,
Viresh Kumar <viresh.kumar@...aro.org>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, fan.chen@...iatek.com,
louis.yu@...iatek.com, roger.lu@...iatek.com,
Allen-yy.Lin@...iatek.com,
Project_Global_Chrome_Upstream_Group@...iatek.com,
hsinyi@...gle.com,
Jia-Wei Chang <jia-wei.chang@...iatek.corp-partner.google.com>
Subject: Re: [PATCH 2/4] dt-bindings: cpufreq: mediatek: add mt8186 cpufreq
dt-bindings
On Mon, Mar 07, 2022 at 08:21:49PM +0800, Tim Chang wrote:
> 1. add cci property.
> 2. add example of MT8186.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@...iatek.corp-partner.google.com>
> ---
> .../bindings/cpufreq/cpufreq-mediatek.yaml | 41 +++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> index 584946eb3790..d3ce17fd8fcf 100644
> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
> @@ -48,6 +48,10 @@ properties:
> When absent, the voltage scaling flow is handled by hardware, hence no
> software "voltage tracking" is needed.
>
> + cci:
> + description:
> + Phandle of the cci to be linked with the phandle of CPU if present.
We already have a binding for this. See cci-control-port.
> +
> "#cooling-cells":
> description:
> For details, please refer to
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