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Message-ID: <ecfe1f3b-3eb7-6676-6f1d-4403b7365ea0@canonical.com>
Date: Thu, 10 Mar 2022 10:25:25 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To: Qin Jian <qinjian@...lus1.com>, robh+dt@...nel.org
Cc: mturquette@...libre.com, sboyd@...nel.org, tglx@...utronix.de,
maz@...nel.org, p.zabel@...gutronix.de, linux@...linux.org.uk,
broonie@...nel.org, arnd@...db.de, stefan.wahren@...e.com,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v10 06/10] clk: Add Sunplus SP7021 clock driver
On 10/03/2022 07:28, Qin Jian wrote:
> Add clock driver for Sunplus SP7021 SoC.
>
> Signed-off-by: Qin Jian <qinjian@...lus1.com>
> ---
> Refine the macro DBG_CLK
> Refine the clock_parent_data
> ---
> MAINTAINERS | 1 +
> drivers/clk/Kconfig | 10 +
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-sp7021.c | 741 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 753 insertions(+)
> create mode 100644 drivers/clk/clk-sp7021.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 90ebb823f..5069f552f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2663,6 +2663,7 @@ W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
> F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml
> F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml
> F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml
> +F: drivers/clk/clk-sp7021.c
> F: drivers/reset/reset-sunplus.c
> F: include/dt-bindings/clock/sp-sp7021.h
> F: include/dt-bindings/reset/sp-sp7021.h
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index c5b3dc973..39751f9b9 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -334,6 +334,16 @@ config COMMON_CLK_VC5
> This driver supports the IDT VersaClock 5 and VersaClock 6
> programmable clock generators.
>
> +config COMMON_CLK_SP7021
> + bool "Clock driver for Sunplus SP7021 SoC"
> + depends on SOC_SP7021 || COMPILE_TEST
> + default SOC_SP7021
> + help
> + This driver supports the Sunplus SP7021 SoC clocks.
> + It implements SP7021 PLLs/gate.
> + Not all features of the PLL are currently supported
> + by the driver.
> +
> config COMMON_CLK_STM32MP157
> def_bool COMMON_CLK && MACH_STM32MP157
> help
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index e42312121..f15bb5070 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -60,6 +60,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
> obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
> obj-$(CONFIG_COMMON_CLK_SI544) += clk-si544.o
> obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
> +obj-$(CONFIG_COMMON_CLK_SP7021) += clk-sp7021.o
> obj-$(CONFIG_COMMON_CLK_STM32F) += clk-stm32f4.o
> obj-$(CONFIG_COMMON_CLK_STM32H7) += clk-stm32h7.o
> obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o
> diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c
> new file mode 100644
> index 000000000..35ae19d65
> --- /dev/null
> +++ b/drivers/clk/clk-sp7021.c
> @@ -0,0 +1,741 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (C) Sunplus Technology Co., Ltd.
> + * All rights reserved.
> + */
> +//#define DEBUG
No dead code, please.
Best regards,
Krzysztof
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