linux-kernel - Re: [RFC PATCH v0 0/6] x86/AMD: Userspace address tagging

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Message-ID: <cc8df752-e92d-3848-8130-d3c48f5a4302@intel.com>
Date:   Fri, 11 Mar 2022 08:51:10 -0800
From:   Dave Hansen <dave.hansen@...el.com>
To:     David Laight <David.Laight@...LAB.COM>,
        'Bharata B Rao' <bharata@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Cc:     "linux-mm@...ck.org" <linux-mm@...ck.org>,
        "x86@...nel.org" <x86@...nel.org>,
        "kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>,
        "dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will@...nel.org" <will@...nel.org>,
        "shuah@...nel.org" <shuah@...nel.org>,
        "oleg@...hat.com" <oleg@...hat.com>,
        "ananth.narayan@....com" <ananth.narayan@....com>
Subject: Re: [RFC PATCH v0 0/6] x86/AMD: Userspace address tagging

On 3/11/22 01:36, David Laight wrote:
> Wikipedia also notes:
>     Intel has implemented a scheme with a 5-level page table, which allows
>     Intel 64 processors to support a 57-bit virtual address space.
>     Further extensions may allow full 64-bit virtual address space and
>     physical memory by expanding the page table entry size to 128-bit,
>     and reduce page walks in the 5-level hierarchy by using a larger 64 KiB
>     page allocation size that still supports 4 KiB page operations for
>     backward compatibility.
> If they implement 64K pages then you lose the extra bits.

I can't believe I need to say this:  Wikipedia is not an authoritative
source about what anyone is going to do with their CPUs in the future.
Please don't base any Linux decisions off this information.