linux-kernel - [PATCH] pinctrl: tegra: Set SFIO mode to Mux Register

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Message-ID: <20220311043015.4027-1-pshete@nvidia.com>
Date:   Fri, 11 Mar 2022 10:00:15 +0530
From:   Prathamesh Shete <pshete@...dia.com>
To:     <linus.walleij@...aro.org>, <thierry.reding@...il.com>,
        <jonathanh@...dia.com>, <linux-gpio@...r.kernel.org>,
        <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC:     <pshete@...dia.com>, <smangipudi@...dia.com>,
        EJ Hsu <ejh@...dia.com>
Subject: [PATCH] pinctrl: tegra: Set SFIO mode to Mux Register

If the device has the 'sfsel' bit field, pin should be
muxed to set to SFIO mode to be used for pinmux operation.

Signed-off-by: EJ Hsu <ejh@...dia.com>
Signed-off-by: Prathamesh Shete <pshete@...dia.com>
---
 drivers/pinctrl/tegra/pinctrl-tegra.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 50bd26a30ac0..30341c43da59 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -270,6 +270,9 @@ static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 	val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 	val &= ~(0x3 << g->mux_bit);
 	val |= i << g->mux_bit;
+	/* Set the SFIO/GPIO selection to SFIO when under pinmux control*/
+	if (pmx->soc->sfsel_in_mux)
+		val |= (1 << g->sfsel_bit);
 	pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 
 	return 0;
-- 
2.17.1