| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Fri, 11 Mar 2022 13:26:29 +0000
From: Mark Brown <broonie@...nel.org>
To: Colin Foster <colin.foster@...advantage.com>
Cc: linux-kernel@...r.kernel.org
Subject: Re: Asymmetric regmap read/write reg
On Thu, Mar 10, 2022 at 01:54:08PM -0800, Colin Foster wrote:
> The Ocelot chip has requires 100ns between address write and when the
> address is ready to be clocked out. This can be dealt with in three
> different ways:
> 1. Use a slow enough clock speed
> 2. Use a delay between address write and value read
> 3. Clock out N padding bytes to account for the 100ns access time
>
> Forcing a slow clock speed is obviously not ideal, and forcing a delay
> between "write_then_read" sounds too driver-specific, so option 3 seems
> like the best option - especially if bulk reads are utilized.
>
> Where regmap comes in is specifically the padding bytes. Reads require
Why not implement this using a delay? That seems both more
straightforward and likely tending to be more accurate given that clock
rates for SPI devices tend to be a bit vague. Much less disruptive to
implement too.
Download attachment "signature.asc" of type "application/pgp-signature" (489 bytes)
Powered by blists - more mailing lists