linux-kernel - Re: [PATCH 4/4] dt-bindings: gnss: Add two more chips

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Message-ID: <f21f4914-0d70-f176-717d-daefc0305d3a@kernel.org>
Date:   Sat, 12 Mar 2022 12:44:29 +0100
From:   Krzysztof Kozlowski <krzk@...nel.org>
To:     Linus Walleij <linus.walleij@...aro.org>,
        Johan Hovold <johan@...nel.org>
Cc:     linux-kernel@...r.kernel.org, devicetree@...r.kernel.org
Subject: Re: [PATCH 4/4] dt-bindings: gnss: Add two more chips

On 12/03/2022 00:51, Linus Walleij wrote:
> The CSR GSD4t is a CSR product using the SiRFstarIV core, and
> the CSR CSRG05TA03-ICJE-R is a CSR product using the SiRFstarV
> core.
> 
> These chips have a SRESETN line that can be pulled low to hard
> reset the chip and in some designs this is connected to a GPIO,
> so add this as an optional property.
> 
> Update the example with a reset line so users see that it need
> to be tagged as active low.
> 
> Cc: devicetree@...r.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@...aro.org>
> ---
>  Documentation/devicetree/bindings/gnss/sirfstar.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/gnss/sirfstar.yaml b/Documentation/devicetree/bindings/gnss/sirfstar.yaml
> index 91874241d0f3..e2ad1f01f9f3 100644
> --- a/Documentation/devicetree/bindings/gnss/sirfstar.yaml
> +++ b/Documentation/devicetree/bindings/gnss/sirfstar.yaml
> @@ -25,6 +25,8 @@ description:
>  properties:
>    compatible:
>      enum:
> +      - csr,gsd4t
> +      - csr,csrg05ta03-icje-r
>        - fastrax,uc430
>        - linx,r4
>        - wi2wi,w2sg0004
> @@ -39,6 +41,10 @@ properties:
>      description:
>        Main voltage regulator, pin names such as 3V3_IN, VCC, VDD.
>  
> +  reset-gpios:
> +    description: An optional active low reset line, should be flagged with
> +      GPIO_ACTIVE_LOW.
> +

maxItems

Best regards,
Krzysztof