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Message-ID: <Yiyvm1/qdYxFoN+a@zn.tnic>
Date: Sat, 12 Mar 2022 15:35:07 +0100
From: Borislav Petkov <bp@...e.de>
To: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Peter Zijlstra <peterz@...radead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/1] tools headers cpufeatures: Sync with the kernel
sources
On Sat, Mar 12, 2022 at 10:37:33AM -0300, Arnaldo Carvalho de Melo wrote:
> FYI, I'm carrying this on the perf tools tree,
>
> Regards,
>
> - Arnaldo
>
> ---
>
> To pick the changes from:
>
> d45476d983240937 ("x86/speculation: Rename RETPOLINE_AMD to RETPOLINE_LFENCE")
>
> Its just a comment fixup.
>
> This only causes these perf files to be rebuilt:
>
> CC /tmp/build/perf/bench/mem-memcpy-x86-64-asm.o
> CC /tmp/build/perf/bench/mem-memset-x86-64-asm.o
>
> And addresses this perf build warning:
>
> Warning: Kernel ABI header at 'tools/arch/x86/include/asm/cpufeatures.h' differs from latest version at 'arch/x86/include/asm/cpufeatures.h'
> diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
>
> Cc: Borislav Petkov <bp@...e.de>
> Cc: Peter Zijlstra (Intel) <peterz@...radead.org>
> Link: https://lore.kernel.org/lkml/
> Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
> ---
> tools/arch/x86/include/asm/cpufeatures.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
> index ab4e53715d8ad8ae..65d147974f8d95e6 100644
> --- a/tools/arch/x86/include/asm/cpufeatures.h
> +++ b/tools/arch/x86/include/asm/cpufeatures.h
> @@ -204,7 +204,7 @@
> /* FREE! ( 7*32+10) */
> #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
> #define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
> -#define X86_FEATURE_RETPOLINE_LFENCE ( 7*32+13) /* "" Use LFENCEs for Spectre variant 2 */
> +#define X86_FEATURE_RETPOLINE_LFENCE ( 7*32+13) /* "" Use LFENCE for Spectre variant 2 */
> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
> #define X86_FEATURE_CDP_L2 ( 7*32+15) /* Code and Data Prioritization L2 */
> #define X86_FEATURE_MSR_SPEC_CTRL ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
> --
ACK.
Thx.
--
Regards/Gruss,
Boris.
SUSE Software Solutions Germany GmbH, GF: Ivo Totev, HRB 36809, AG Nürnberg
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