[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20220312230526.2581-1-miles.chen@mediatek.com>
Date: Sun, 13 Mar 2022 07:05:26 +0800
From: Miles Chen <miles.chen@...iatek.com>
To: <chun-jie.chen@...iatek.com>
CC: <Project_Global_Chrome_Upstream_Group@...iatek.com>,
<devicetree@...r.kernel.org>, <drinkcat@...omium.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <matthias.bgg@...il.com>,
<robh+dt@...nel.org>, <sboyd@...nel.org>,
<srv_heupstream@...iatek.com>
Subject: Re: [PATCH v3 05/15] clk: mediatek: Add MT8186 apmixedsys clock support
> Add MT8186 apmixedsys clock controller which provides Plls
> generated from SoC.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@...iatek.com>
> Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Reviewed-by: Miles Chen <miles.chen@...iatek.com>
Powered by blists - more mailing lists