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Message-ID: <BN0PR02MB8173C4634F3738916E5A4334E40F9@BN0PR02MB8173.namprd02.prod.outlook.com>
Date:   Mon, 14 Mar 2022 14:49:47 +0000
From:   Vinod Polimera <vpolimer@....qualcomm.com>
To:     "dmitry.baryshkov@...aro.org" <dmitry.baryshkov@...aro.org>,
        quic_vpolimer <quic_vpolimer@...cinc.com>
CC:     "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
        "linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
        "freedreno@...ts.freedesktop.org" <freedreno@...ts.freedesktop.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "robdclark@...il.com" <robdclark@...il.com>,
        "dianders@...omium.org" <dianders@...omium.org>,
        "swboyd@...omium.org" <swboyd@...omium.org>,
        quic_kalyant <quic_kalyant@...cinc.com>
Subject: RE: [PATCH v5 5/5] drm/msm/disp/dpu1: set mdp clk to the maximum
 frequency in opp table during probe



> -----Original Message-----
> From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Sent: Tuesday, March 8, 2022 10:40 PM
> To: quic_vpolimer <quic_vpolimer@...cinc.com>
> Cc: dri-devel@...ts.freedesktop.org; linux-arm-msm@...r.kernel.org;
> freedreno@...ts.freedesktop.org; devicetree@...r.kernel.org; linux-
> kernel@...r.kernel.org; robdclark@...il.com; dianders@...omium.org;
> swboyd@...omium.org; quic_kalyant <quic_kalyant@...cinc.com>
> Subject: Re: [PATCH v5 5/5] drm/msm/disp/dpu1: set mdp clk to the
> maximum frequency in opp table during probe
> 
> WARNING: This email originated from outside of Qualcomm. Please be wary
> of any links or attachments, and do not enable macros.
> 
> On Tue, 8 Mar 2022 at 19:55, Vinod Polimera <quic_vpolimer@...cinc.com>
> wrote:
> >
> > use max clock during probe/bind sequence from the opp table.
> > The clock will be scaled down when framework sends an update.
> >
> > Signed-off-by: Vinod Polimera <quic_vpolimer@...cinc.com>
> > ---
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > index d550f90..d9922b9 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> > @@ -1221,6 +1221,7 @@ static int dpu_bind(struct device *dev, struct
> device *master, void *data)
> >         struct dpu_kms *dpu_kms;
> >         struct dss_module_power *mp;
> >         int ret = 0;
> > +       unsigned long max_freq = ULONG_MAX;
> >
> >         dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms),
> GFP_KERNEL);
> >         if (!dpu_kms)
> > @@ -1243,6 +1244,8 @@ static int dpu_bind(struct device *dev, struct
> device *master, void *data)
> >                 return ret;
> >         }
> >
> > +       dev_pm_opp_find_freq_floor(dev, &max_freq);
> 
> You leak a reference to the opp here. The function returns a value,
> which should be dev_pm_opp_put().
> Moreover judging from the dev_pm_opp_set_rate() code I think you don't
> have to find an exact frequency, as it will call
> clk_round_rate()/_find_freq_ceil() anyway.
> Could you please check that it works?

clk_round_rate  will get the max frequency in freq_table in clk driver and if that frequency is missing in opp
table it will throw error. So, It will be optimal to get max freq in opp table and set it based on that freq.
> 
> > +       dev_pm_opp_set_rate(dev, max_freq);
> >         platform_set_drvdata(pdev, dpu_kms);
> >
> >         ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
> > --
> > 2.7.4
> >
> 
> 
> --
> With best wishes
> Dmitry

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