linux-kernel - Re: [PATCH 2/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY

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Message-ID: <e7765c888e6fc8eb4b15fa01d19afda335b16c26.camel@mediatek.com>
Date:   Mon, 14 Mar 2022 09:42:15 +0800
From:   Jianjun Wang <jianjun.wang@...iatek.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Chunfeng Yun <chunfeng.yun@...iatek.com>,
        Kishon Vijay Abraham I <kishon@...com>,
        "Vinod Koul" <vkoul@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-phy@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <rex-bc.chen@...iatek.com>,
        <randy.wu@...iatek.com>, <jieyy.yang@...iatek.com>,
        <chuanjia.liu@...iatek.com>, <qizhong.cheng@...iatek.com>,
        <jian.yang@...iatek.com>
Subject: Re: [PATCH 2/2] dt-bindings: phy: mediatek: Add YAML schema for
 PCIe PHY

Hi Krzysztof,

On Fri, 2022-03-11 at 15:28 +0100, Krzysztof Kozlowski wrote:
> On 11/03/2022 14:35, Jianjun Wang wrote:
> > Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
> > 
> > Signed-off-by: Jianjun Wang <jianjun.wang@...iatek.com>
> > ---
> >  .../bindings/phy/mediatek,pcie-phy.yaml       | 71
> > +++++++++++++++++++
> >  1 file changed, 71 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-
> > phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-
> > phy.yaml
> > new file mode 100644
> > index 000000000000..da15b4bf3117
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek PCIe PHY Device Tree Binding
> 
> Title is for hardware, so s/Device Tree Binding//
> 
> > +
> > +maintainers:
> > +  - Jianjun Wang <jianjun.wang@...iatek.com>
> > +
> > +description: |
> > +  The PCIe PHY supports physical layer functionality for PCIe Gen3
> > port.
> > +
> > +properties:
> > +  compatible:
> > +    const: mediatek,pcie-phy
> 
> Is it going to be exactly one pcie-phy for all Mediatek chipsets for
> next years? Are you sure about that? It sounds highly unlikely....

We have only one pcie-phy for now, but if this is not recommended, I
will replace it with a specific name in the next version, thanks for
your review.

Thanks.

> 
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  reg-names:
> > +    items:
> > +      - const: sif
> > +
> > +  "#phy-cells":
> > +    const: 0
> > +
> > +  nvmem-cells:
> > +    maxItems: 7
> > +    description:
> > +      Phandles to nvmem cell that contains the efuse data, if
> > unspecified,
> > +      default value is used.
> > +
> > +  nvmem-cell-names:
> > +    items:
> > +      - const: glb_intr
> > +      - const: tx_ln0_pmos
> > +      - const: tx_ln0_nmos
> > +      - const: rx_ln0
> > +      - const: tx_ln1_pmos
> > +      - const: tx_ln1_nmos
> > +      - const: rx_ln1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +  - "#phy-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    pciephy: phy@...80000 {
> > +        compatible = "mediatek,pcie-phy";
> > +        #phy-cells = <0>;
> > +        reg = <0x11e80000 0x10000>;
> > +        reg-names = "sif";
> > +        nvmem-cells = <&pciephy_glb_intr>,
> > +                      <&pciephy_tx_ln0_pmos>,
> > +                      <&pciephy_tx_ln0_nmos>,
> > +                      <&pciephy_rx_ln0>,
> > +                      <&pciephy_tx_ln1_pmos>,
> > +                      <&pciephy_tx_ln1_nmos>,
> > +                      <&pciephy_rx_ln1>;
> > +        nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
> > +                           "tx_ln0_nmos", "rx_ln0",
> > +                           "tx_ln1_pmos", "tx_ln1_nmos",
> > +                           "rx_ln1";
> > +    };
> 
> 
> Best regards,
> Krzysztof