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Message-ID: <20220315170507.GH11336@nvidia.com>
Date:   Tue, 15 Mar 2022 14:05:07 -0300
From:   Jason Gunthorpe <jgg@...dia.com>
To:     Jacob Pan <jacob.jun.pan@...ux.intel.com>
Cc:     Robin Murphy <robin.murphy@....com>,
        iommu@...ts.linux-foundation.org,
        LKML <linux-kernel@...r.kernel.org>,
        Joerg Roedel <joro@...tes.org>,
        Christoph Hellwig <hch@...radead.org>,
        Lu Baolu <baolu.lu@...ux.intel.com>,
        Jean-Philippe Brucker <jean-philippe@...aro.com>,
        "Tian, Kevin" <kevin.tian@...el.com>,
        Tony Luck <tony.luck@...el.com>,
        Dave Jiang <dave.jiang@...el.com>,
        Raj Ashok <ashok.raj@...el.com>,
        "Zanussi, Tom" <tom.zanussi@...el.com>,
        "Kumar, Sanjay K" <sanjay.k.kumar@...el.com>,
        Jacob Pan <jacob.jun.pan@...el.com>,
        Dan Williams <dan.j.williams@...el.com>
Subject: Re: [PATCH v2 5/8] iommu: Add PASID support for DMA mapping API users

On Tue, Mar 15, 2022 at 09:31:35AM -0700, Jacob Pan wrote:

> > IMHO it is a device mis-design of IDXD to require all DMA be PASID
> > tagged. Devices should be able to do DMA on their RID when the PCI

> IDXD can do DMA w/ RID, the PASID requirement is only for shared WQ where
> ENQCMDS is used. ENQCMDS has the benefit of avoiding locking where work
> submission is done from multiple CPUs.
> Tony, Dave?

This is what I mean, it has an operating mode you want to use from the
kernel driver that cannot do RID DMA. It is a HW mis-design, IMHO.

Something like PASID0 in the ENQCMDS should have triggered RID DMA.

> > In any case I think we are better to wait for an actual user for multi
> > DMA API iommu_domains to come forward before we try to build an API
> > for it.
> 
> What would you recommend in the interim?

Oh, I mean this approach at a high level is fine - I was saying we
shouldn't try to broaden it like Robin was suggesting without a driver
that needs multiple iommu_domains for the DMA API.

Jason

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