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Message-ID: <c8670520-e767-d0ec-b17b-5279ffa61450@amd.com>
Date: Tue, 15 Mar 2022 16:46:30 -0500
From: "Koralahalli Channabasappa, Smita" <skoralah@....com>
To: Borislav Petkov <bp@...en8.de>, Tony Luck <tony.luck@...el.com>
Cc: Smita Koralahalli <Smita.KoralahalliChannabasappa@....com>,
hpa@...or.com, Dave Hansen <dave.hansen@...ux.intel.com>,
Yazen Ghannam <yazen.ghannam@....com>,
linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
patches@...ts.linux.dev
Subject: Re: [PATCH v2 0/2] New CMCI storm mitigation for Intel CPUs
On 3/15/22 1:34 PM, Borislav Petkov wrote:
> On Tue, Mar 15, 2022 at 11:15:07AM -0700, Tony Luck wrote:
>> Smita: Unless Boris finds a some more stuff for me to fix, this
>> version will be a better starting point to merge with your changes.
> Right, I'm wondering if AMD can use the same scheme so that abstracting
> out the hw-specific accesses (MSR writes, etc) would be enough...
Thanks Tony.
Agreed. Most of this would apply for AMD's threshold interrupts too.
Will come up with a merged patch and move the storm handling to
mce/core.c and just keep the hw-specific accesses separate for
Intel and AMD in their respective files.
Thanks
Smita.
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