linux-kernel - Re: [PATCH] [v1] arch: arm: configs: gxp

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Message-ID: <483082A1-A464-4D3D-B994-66B09E5D54B5@hpe.com>
Date:   Wed, 16 Mar 2022 18:54:15 +0000
From:   "Verdun, Jean-Marie" <verdun@....com>
To:     Arnd Bergmann <arnd@...db.de>
CC:     "Hawkins, Nick" <nick.hawkins@....com>,
        Russell King <linux@...linux.org.uk>,
        Joel Stanley <joel@....id.au>,
        Andrew Jeffery <andrew@...id.au>,
        Olof Johansson <olof@...om.net>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] [v1] arch: arm: configs: gxp_defconfig

Hi,

>    If you get unknown instruction exceptions, that is clearly a bug that has to be
>    fixed somewhere. Turning the options off should not be necessary, but we have
>    to figure out why these crash, and make sure we have correct runtime detection
>    in place that ensures that any driver code runs only on platforms that have the
>    corresponding hardware.

>    Do you have any more information about how and why these crash? My first
>    guess would be that there is something in your DT that describes hardware
>    that is not actually there. With a correct DTB file, the two options should
>    not cause any code to run that wouldn't otherwise.

I think I found part of the issue regarding the PERF_EVENTS. In ./arch/arm/kernel/hw_breakpoint.c, the function core_has_os_save_restore is calling the mrc p14 instruction to determine ARM_OSLSR_OSLM0 value. Unfortunately per the ARM Cortex A9 documentation that call is not implemented on such core
( https://developer.arm.com/documentation/ddi0388/i/debug/debug-register-summary )

which is leading to an unknown instruction on our ASIC.

Need to figuring out how to workaround that. I will check what ARM_DEBUG_ARCH_V7_ECP14 is supposed to support. We might have either a bug into the way we report the ASIC id or something is weird into the kernel which is assuming that Cortex A9 support this PMU access.

vejmarie