linux-kernel - [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220316092525.4554-4-amhetre@nvidia.com>
Date:   Wed, 16 Mar 2022 14:55:24 +0530
From:   Ashish Mhetre <amhetre@...dia.com>
To:     <krzysztof.kozlowski@...onical.com>, <robh+dt@...nel.org>,
        <thierry.reding@...il.com>, <digetx@...il.com>,
        <jonathanh@...dia.com>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>
CC:     <vdumpa@...dia.com>, <Snikam@...dia.com>, <amhetre@...dia.com>
Subject: [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186

>From tegra186 onwards, memory controller support multiple channels.
Reg items are updated with address and size of these channels.
Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234
have overall 17 memory controller channels each.
There is 1 reg item for memory controller stream-id registers.
So update the reg maxItems to 18 in tegra186 devicetree documentation.

Signed-off-by: Ashish Mhetre <amhetre@...dia.com>
---
 .../nvidia,tegra186-mc.yaml                   | 20 +++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 13c4c82fd0d3..3c4e231dc1de 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -34,8 +34,8 @@ properties:
           - nvidia,tegra234-mc
 
   reg:
-    minItems: 1
-    maxItems: 3
+    minItems: 6
+    maxItems: 18
 
   interrupts:
     items:
@@ -142,7 +142,8 @@ allOf:
     then:
       properties:
         reg:
-          maxItems: 1
+          maxItems: 6
+          description: 5 memory controller channels and 1 for stream-id registers
 
   - if:
       properties:
@@ -151,7 +152,8 @@ allOf:
     then:
       properties:
         reg:
-          minItems: 3
+          minItems: 18
+          description: 17 memory controller channels and 1 for stream-id registers
 
   - if:
       properties:
@@ -160,7 +162,8 @@ allOf:
     then:
       properties:
         reg:
-          minItems: 3
+          minItems: 18
+          description: 17 memory controller channels and 1 for stream-id registers
 
 additionalProperties: false
 
@@ -198,7 +201,12 @@ examples:
 
             external-memory-controller@...0000 {
                 compatible = "nvidia,tegra186-emc";
-                reg = <0x0 0x02c60000 0x0 0x50000>;
+                reg = <0x0 0x02c00000 0x0 0x10000>,    /* MC-SID */
+                      <0x0 0x02c10000 0x0 0x10000>,    /* Broadcast channel */
+                      <0x0 0x02c20000 0x0 0x10000>,    /* MC0 */
+                      <0x0 0x02c30000 0x0 0x10000>,    /* MC1 */
+                      <0x0 0x02c40000 0x0 0x10000>,    /* MC2 */
+                      <0x0 0x02c50000 0x0 0x10000>;    /* MC3 */
                 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&bpmp TEGRA186_CLK_EMC>;
                 clock-names = "emc";
-- 
2.17.1