linux-kernel - Re: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220316124208.GA310478@leoy-ThinkPad-X240s>
Date:   Wed, 16 Mar 2022 20:42:08 +0800
From:   Leo Yan <leo.yan@...aro.org>
To:     German Gomez <german.gomez@....com>
Cc:     Ali Saidi <alisaidi@...zon.com>, acme@...nel.org,
        alexander.shishkin@...ux.intel.com, andrew.kilroy@....com,
        benh@...nel.crashing.org, james.clark@....com,
        john.garry@...wei.com, jolsa@...nel.org, kjain@...ux.ibm.com,
        lihuafei1@...wei.com, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
        mark.rutland@....com, mathieu.poirier@...aro.org, mingo@...hat.com,
        namhyung@...nel.org, peterz@...radead.org, will@...nel.org,
        yao.jin@...ux.intel.com, Nick.Forrington@....com
Subject: Re: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is
 used

On Wed, Mar 16, 2022 at 11:43:52AM +0000, German Gomez wrote:

[...]

> >>> I had a look at the TRMs for the N1[1], V1[2] and N2[3] Neoverse cores
> >>> (specifically the LL_CACHE_RD pmu events). If we were to assign a number
> >>> to the system cache (assuming all caches are implemented):
> >>>
> >>> *For N1*, if L2 and L3 are implemented, system cache would follow at *L4*
> >> To date no one has built 4 level though. Everyone has only built three.
> > The N1SDP board advertises 4 levels (we use it regularly for testing perf patches)
> 
> That said, it's probably the odd one out.
> 
> I'm not against assuming 3 levels. Later if there's is a strong need for L4, indeed we can go back and change it.

Thanks for the info.

For exploring cache hierarchy via sysFS is a good idea, the only one
concern for me is: can we simply take the system cache as the same
thing as the highest level cache?  If so, I think another option is to
define a cache level as "PERF_MEM_LVLNUM_SYSTEM_CACHE" and extend the
decoding code for support it.

With PERF_MEM_LVLNUM_SYSTEM_CACHE, it can tell users clearly the data
source from system cache, and users can easily map this info with the
cache media on the working platform.

In practice, I don't object to use cache level 3 at first step.  At
least this can meet the requirement at current stage.

Thanks,
Leo