linux-kernel - Re: [RFC PATCH v4 0/5] Renesas RZ/G2L IRQC support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 17 Mar 2022 09:23:08 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Rob Herring <robh+dt@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <brgl@...ev.pl>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        Prabhakar <prabhakar.csengg@...il.com>,
        Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [RFC PATCH v4 0/5] Renesas RZ/G2L IRQC support

On Thu, 17 Mar 2022 08:46:14 +0000,
Andy Shevchenko <andy.shevchenko@...il.com> wrote:
> 
> On Thu, Mar 17, 2022 at 5:43 AM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> >
> > Hi All,
> >
> > The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> > Renesas RZ/G2L SoC's with below pins:
> > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
> > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
> >   maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> > - NMI edge select.
> >
> What I want to know now is whether it is going to collide with Marc's
> series about GPIO IRQ chip constification?

Probably, but the current scheme will still be alive for some time
(you'll need a couple of cycles to sort out all the drivers).

Worse case, this can be fixed at merge time.

	M.

-- 
Without deviation from the norm, progress is not possible.