linux-kernel - [irqchip: irq/irqchip-next] pinctrl: npcm: Fix broken typing on 64bit platforms

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Date:   Thu, 17 Mar 2022 09:47:27 -0000
From:   "irqchip-bot for Stephen Rothwell" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Stephen Rothwell <sfr@...b.auug.org.au>,
        Marc Zyngier <maz@...nel.org>, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] pinctrl: npcm: Fix broken typing on 64bit
 platforms

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     1c3b5c62fc856e8ba71f071d1cf37b2d88411e8b
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/1c3b5c62fc856e8ba71f071d1cf37b2d88411e8b
Author:        Stephen Rothwell <sfr@...b.auug.org.au>
AuthorDate:    Wed, 16 Mar 2022 18:12:14 +11:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Thu, 17 Mar 2022 08:20:39 

pinctrl: npcm: Fix broken typing on 64bit platforms

The npcm driver confuses u32 and unsigned long, which works on
32bit platforms, but leads to disasters on 64bit systems (and
breaks the build if using -Werror=array-bounds).

Use proper typing to address the issue.

Signed-off-by: Stephen Rothwell <sfr@...b.auug.org.au>
[maz: commit message, additional changes suggested by Jonathan Neuschäfer]
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20220316183227.725bfd37@canb.auug.org.au
---
 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
index ba536fd..a9831da 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
@@ -216,7 +216,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc)
 	struct gpio_chip *gc;
 	struct irq_chip *chip;
 	struct npcm7xx_gpio *bank;
-	u32 sts, en, bit;
+	unsigned long sts, bit, en;
 
 	gc = irq_desc_get_handler_data(desc);
 	bank = gpiochip_get_data(gc);
@@ -225,11 +225,11 @@ static void npcmgpio_irq_handler(struct irq_desc *desc)
 	chained_irq_enter(chip, desc);
 	sts = ioread32(bank->base + NPCM7XX_GP_N_EVST);
 	en  = ioread32(bank->base + NPCM7XX_GP_N_EVEN);
-	dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts,
+	dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts,
 		en);
 
 	sts &= en;
-	for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK)
+	for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK)
 		generic_handle_domain_irq(gc->irq.domain, bit);
 	chained_irq_exit(chip, desc);
 }