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Message-Id: <20220317124526.168543089@linuxfoundation.org>
Date: Thu, 17 Mar 2022 13:45:48 +0100
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org, Dinh Nguyen <dinguyen@...nel.org>,
Sasha Levin <sashal@...nel.org>
Subject: [PATCH 5.10 07/23] arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
From: Dinh Nguyen <dinguyen@...nel.org>
[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]
The DWC2 USB controller on the Agilex platform does not support clock
gating, so use the chip specific "intel,socfpga-agilex-hsotg"
compatible.
Signed-off-by: Dinh Nguyen <dinguyen@...nel.org>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 07c099b4ed5b..1e0c9415bfcd 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -476,7 +476,7 @@
};
usb0: usb@...00000 {
- compatible = "snps,dwc2";
+ compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb00000 0x40000>;
interrupts = <0 93 4>;
phys = <&usbphy0>;
@@ -489,7 +489,7 @@
};
usb1: usb@...40000 {
- compatible = "snps,dwc2";
+ compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
reg = <0xffb40000 0x40000>;
interrupts = <0 94 4>;
phys = <&usbphy0>;
--
2.34.1
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