linux-kernel - Re: [PATCH 5/8] perf vendor events: Update events for Skylake

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <b05f4132-14de-579b-528c-5bfe877725ae@linux.intel.com>
Date:   Fri, 18 Mar 2022 17:19:46 +0800
From:   Xing Zhengjun <zhengjun.xing@...ux.intel.com>
To:     Ian Rogers <irogers@...gle.com>,
        Kan Liang <kan.liang@...ux.intel.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Andi Kleen <ak@...ux.intel.com>,
        James Clark <james.clark@....com>,
        John Garry <john.garry@...wei.com>,
        linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org
Cc:     Stephane Eranian <eranian@...gle.com>
Subject: Re: [PATCH 5/8] perf vendor events: Update events for Skylake



On 3/18/2022 2:28 AM, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache topic. Update the
> perf json files for this change.
> 
> Signed-off-by: Ian Rogers <irogers@...gle.com>

Reviewed-by: Zhengjun Xing <zhengjun.xing@...ux.intel.com>

> ---
>   .../pmu-events/arch/x86/skylake/cache.json    | 36 +++++++++++++++++++
>   .../pmu-events/arch/x86/skylake/other.json    | 36 -------------------
>   2 files changed, 36 insertions(+), 36 deletions(-)
> 
> diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json
> index 529c5e6e117f..c5d9a4ed10d7 100644
> --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json
> @@ -2937,5 +2937,41 @@
>           "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
>           "SampleAfterValue": "100003",
>           "UMask": "0x10"
> +    },
> +    {
> +        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> +        "Counter": "0,1,2,3",
> +        "CounterHTOff": "0,1,2,3,4,5,6,7",
> +        "EventCode": "0x32",
> +        "EventName": "SW_PREFETCH_ACCESS.NTA",
> +        "SampleAfterValue": "2000003",
> +        "UMask": "0x1"
> +    },
> +    {
> +        "BriefDescription": "Number of PREFETCHW instructions executed.",
> +        "Counter": "0,1,2,3",
> +        "CounterHTOff": "0,1,2,3,4,5,6,7",
> +        "EventCode": "0x32",
> +        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> +        "SampleAfterValue": "2000003",
> +        "UMask": "0x8"
> +    },
> +    {
> +        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> +        "Counter": "0,1,2,3",
> +        "CounterHTOff": "0,1,2,3,4,5,6,7",
> +        "EventCode": "0x32",
> +        "EventName": "SW_PREFETCH_ACCESS.T0",
> +        "SampleAfterValue": "2000003",
> +        "UMask": "0x2"
> +    },
> +    {
> +        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> +        "Counter": "0,1,2,3",
> +        "CounterHTOff": "0,1,2,3,4,5,6,7",
> +        "EventCode": "0x32",
> +        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> +        "SampleAfterValue": "2000003",
> +        "UMask": "0x4"
>       }
>   ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json
> index 5c0e81f76a5b..4f4839024915 100644
> --- a/tools/perf/pmu-events/arch/x86/skylake/other.json
> +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json
> @@ -16,41 +16,5 @@
>           "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
>           "SampleAfterValue": "2000003",
>           "UMask": "0x1"
> -    },
> -    {
> -        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> -        "Counter": "0,1,2,3",
> -        "CounterHTOff": "0,1,2,3,4,5,6,7",
> -        "EventCode": "0x32",
> -        "EventName": "SW_PREFETCH_ACCESS.NTA",
> -        "SampleAfterValue": "2000003",
> -        "UMask": "0x1"
> -    },
> -    {
> -        "BriefDescription": "Number of PREFETCHW instructions executed.",
> -        "Counter": "0,1,2,3",
> -        "CounterHTOff": "0,1,2,3,4,5,6,7",
> -        "EventCode": "0x32",
> -        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> -        "SampleAfterValue": "2000003",
> -        "UMask": "0x8"
> -    },
> -    {
> -        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> -        "Counter": "0,1,2,3",
> -        "CounterHTOff": "0,1,2,3,4,5,6,7",
> -        "EventCode": "0x32",
> -        "EventName": "SW_PREFETCH_ACCESS.T0",
> -        "SampleAfterValue": "2000003",
> -        "UMask": "0x2"
> -    },
> -    {
> -        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> -        "Counter": "0,1,2,3",
> -        "CounterHTOff": "0,1,2,3,4,5,6,7",
> -        "EventCode": "0x32",
> -        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> -        "SampleAfterValue": "2000003",
> -        "UMask": "0x4"
>       }
>   ]
> \ No newline at end of file

-- 
Zhengjun Xing