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Message-Id: <20220318111742.15730-3-sherry.sun@nxp.com>
Date: Fri, 18 Mar 2022 19:17:42 +0800
From: Sherry Sun <sherry.sun@....com>
To: bp@...en8.de, mchehab@...nel.org, michal.simek@...inx.com,
tony.luck@...el.com, james.morse@....com, rric@...nel.org
Cc: linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-imx@....com
Subject: [PATCH 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X Synopsys EDAC DDR
Since zynqmp_get_error_info() is called during CE/UE interrupt, at the
end of zynqmp_get_error_info(), it wirtes 0 to ECC_CLR_OFST, which cause
the CE/UE interrupts of V3.X Synopsys EDAC DDR been disabled, then the
interrupt handler will be called only once, so need to re-enable the
interrupts at the end of intr_handler for V3.X Synopsys EDAC DDR.
Signed-off-by: Sherry Sun <sherry.sun@....com>
---
drivers/edac/synopsys_edac.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 1b630f0be119..3a1db34a8546 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -521,6 +521,8 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
memset(p, 0, sizeof(*p));
}
+static void enable_intr(struct synps_edac_priv *priv);
+
/**
* intr_handler - Interrupt Handler for ECC interrupts.
* @irq: IRQ number.
@@ -562,6 +564,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
/* v3.0 of the controller does not have this register */
if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
+ else
+ enable_intr(priv);
return IRQ_HANDLED;
}
--
2.17.1
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