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Message-ID: <Yjivcz4BlCMfJBkM@C02CK6Q3MD6M>
Date: Mon, 21 Mar 2022 11:01:39 -0600
From: Keith Busch <kbusch@...nel.org>
To: Sven Peter <sven@...npeter.dev>
Cc: Jens Axboe <axboe@...com>, Christoph Hellwig <hch@....de>,
Sagi Grimberg <sagi@...mberg.me>,
Hector Martin <marcan@...can.st>,
Alyssa Rosenzweig <alyssa@...enzweig.io>,
Rob Herring <robh+dt@...nel.org>,
Arnd Bergmann <arnd@...db.de>, Marc Zyngier <maz@...nel.org>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-nvme@...ts.infradead.org
Subject: Re: [PATCH 6/9] nvme-apple: Add initial Apple SoC NVMe driver
On Mon, Mar 21, 2022 at 05:50:46PM +0100, Sven Peter wrote:
> +static bool apple_nvme_poll_cq(struct apple_nvme_queue *q,
> + struct io_comp_batch *iob)
> +{
> + bool found = false;
> +
> + while (apple_nvme_cqe_pending(q)) {
> + found = true;
> +
> + /*
> + * load-load control dependency between phase and the rest of
> + * the cqe requires a full read memory barrier
> + */
> + dma_rmb();
> + apple_nvme_handle_cqe(q, iob, q->cq_head);
> + apple_nvme_update_cq_head(q);
> + }
> +
> + if (found)
> + writel_relaxed(q->cq_head, q->cq_db);
Doesn't a relaxed write mean that a subsequent write can bypass the previous?
If so, that sounds like it can corrupt the cq head.
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