linux-kernel - Re: [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins

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Date:   Mon, 21 Mar 2022 09:15:00 -0500
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Luca Weiss <luca.weiss@...rphone.com>
Cc:     linux-arm-msm@...r.kernel.org,
        ~postmarketos/upstreaming@...ts.sr.ht, phone-devel@...r.kernel.org,
        Andy Gross <agross@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...ainline.org>,
        Konrad Dybcio <konrad.dybcio@...ainline.org>,
        linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins

On Mon 21 Mar 08:33 CDT 2022, Luca Weiss wrote:

> In other places the SDC and UFS pins have been swapped but this was
> missed in the PINCTRL_PIN definitions. Fix that.
> 
> Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver")
> Signed-off-by: Luca Weiss <luca.weiss@...rphone.com>

Your proposed change looks good, but when I look at 7d74b55afd27 it
already has these entries in the correct order.

Can you please confirm that this is still applicable. Or help me see
what I am missing.

Regards,
Bjorn

> ---
> Changes in v2:
> - nothing
> 
>  drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c
> index 4d37b817b232..a91a86628f2f 100644
> --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c
> +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c
> @@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = {
>  	PINCTRL_PIN(153, "GPIO_153"),
>  	PINCTRL_PIN(154, "GPIO_154"),
>  	PINCTRL_PIN(155, "GPIO_155"),
> -	PINCTRL_PIN(156, "SDC1_RCLK"),
> -	PINCTRL_PIN(157, "SDC1_CLK"),
> -	PINCTRL_PIN(158, "SDC1_CMD"),
> -	PINCTRL_PIN(159, "SDC1_DATA"),
> -	PINCTRL_PIN(160, "SDC2_CLK"),
> -	PINCTRL_PIN(161, "SDC2_CMD"),
> -	PINCTRL_PIN(162, "SDC2_DATA"),
> -	PINCTRL_PIN(163, "UFS_RESET"),
> +	PINCTRL_PIN(156, "UFS_RESET"),
> +	PINCTRL_PIN(157, "SDC1_RCLK"),
> +	PINCTRL_PIN(158, "SDC1_CLK"),
> +	PINCTRL_PIN(159, "SDC1_CMD"),
> +	PINCTRL_PIN(160, "SDC1_DATA"),
> +	PINCTRL_PIN(161, "SDC2_CLK"),
> +	PINCTRL_PIN(162, "SDC2_CMD"),
> +	PINCTRL_PIN(163, "SDC2_DATA"),
>  };
>  
>  #define DECLARE_MSM_GPIO_PINS(pin) \
> -- 
> 2.35.1
>