linux-kernel - Re: [PATCH 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling

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Message-ID: <7de451b4-32ff-c8b5-7c69-6440f73b59ae@amd.com>
Date:   Tue, 22 Mar 2022 14:07:58 +0530
From:   Sandipan Das <sandipan.das@....com>
To:     Like Xu <like.xu.linux@...il.com>
Cc:     peterz@...radead.org, bp@...en8.de, dave.hansen@...ux.intel.com,
        acme@...nel.org, mark.rutland@....com,
        alexander.shishkin@...ux.intel.com, namhyung@...nel.org,
        jolsa@...nel.org, tglx@...utronix.de, mingo@...hat.com,
        pbonzini@...hat.com, jmattson@...gle.com, eranian@...gle.com,
        ananth.narayan@....com, ravi.bangoria@....com,
        santosh.shukla@....com,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-perf-users@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH 6/7] perf/x86/amd/core: Add PerfMonV2 overflow handling


On 3/22/2022 12:36 PM, Like Xu wrote:
> On 17/3/2022 2:28 pm, Sandipan Das wrote:
>> +        val = x86_perf_event_update(event);
> 
> The variable 'val' set but not used.
> 
>> +        mask = BIT_ULL(idx);
>> +
>> +        if (!(status & mask))
> 
> Needed here ?
> 

If you are referring to this previous usage of 'val' within
x86_pmu_handle_irq():

  if (val & (1ULL << (x86_pmu.cntval_bits - 1)))

then, no. Instead of looking at bit 47 of the raw counter value,
one can look at the overflow bits of the global status register
to determine if a counter overflow has occurred.

Will remove 'val' as you suggested since it is no longer needed
for any decision making.