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Message-ID: <cb74e44b-5f4e-e644-a952-3872296fefc6@kernel.org>
Date: Wed, 23 Mar 2022 09:54:35 +0200
From: Roger Quadros <rogerq@...nel.org>
To: Aswath Govindraju <a-govindraju@...com>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-usb@...r.kernel.org, Felipe Balbi <balbi@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Vignesh Raghavendra <vigneshr@...com>,
Kishon Vijay Abraham I <kishon@...com>
Subject: Re: [PATCH 1/2] dt-bindings: usb: Add documentation for AM62 USB
Wrapper module
On 23/03/2022 07:35, Aswath Govindraju wrote:
> Add bindings for the TI's AM62 wrapper module for the Synopsys USBSS-DRD
> controller.
>
> Signed-off-by: Aswath Govindraju <a-govindraju@...com>
> ---
> .../devicetree/bindings/usb/ti,am62-usb.yaml | 98 +++++++++++++++++++
> 1 file changed, 98 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/ti,am62-usb.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/ti,am62-usb.yaml b/Documentation/devicetree/bindings/usb/ti,am62-usb.yaml
> new file mode 100644
> index 000000000000..4bb139d1926d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/ti,am62-usb.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Bindings for the TI's AM62 wrapper module for the Synopsys USBSS-DRD controller
> +
> +maintainers:
> + - Aswath Govindraju <a-govindraju@...com>
> +
> +properties:
> + compatible:
> + const: ti,am62-usb
> +
> + reg:
> + maxItems: 1
> +
> + ranges: true
> +
> + power-domains:
> + description:
> + PM domain provider node and an args specifier containing
> + the USB ISO device id value. See,
> + Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
> + maxItems: 1
> +
> + clocks:
> + description: Clock phandles to usb2_refclk
s/phandles/phandle
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: ref
> +
> + id-gpio:
> + description:
> + GPIO to be used as ID pin
> + maxItems: 1
> +
> + interrupts:
> + description:
> + interrupt line to be used for detecting changes in VBUS
maxItems: 1 ?
> +
> + ti,vbus-divider:
> + description:
> + Should be present if USB VBUS line is connected to the
> + VBUS pin of the SoC via a 1/3 voltage divider.
> + type: boolean
> +
> + ti,syscon-phy-pll-refclk:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + - items:
> + - description: Phandle to the SYSCON entry
> + - description: USB phy control register offset within SYSCON
> + description: Specifier for configuring frequency of ref clock input.
> +
> + '#address-cells':
> + const: 2
> +
> + '#size-cells':
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - power-domains
> + - clocks
> + - clock-names
> + - interrupts
> + - ti,syscon-phy-pll-refclk
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/soc/ti,sci_pm_domain.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/gpio/gpio.h>
> +
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + dwc3-usb@...0000 {
> + compatible = "ti,am62-usb";
> + reg = <0x00 0x0f910000 0x00 0x800>;
> + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; /* MISC IRQ */
> + clocks = <&k3_clks 162 3>;
> + clock-names = "ref";
> + ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
> + power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
> + id-gpio = <&main_gpio1 51 GPIO_ACTIVE_LOW>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + };
> + };
Reviewed-by: Roger Quadros <rogerq@...nel.org>
cheers,
-roger
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