linux-kernel - Re: [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward

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Message-ID: <4e07bee8-d3b2-daf4-b107-780e90b5d720@nvidia.com>
Date:   Wed, 23 Mar 2022 14:06:38 +0530
From:   Ashish Mhetre <amhetre@...dia.com>
To:     Dmitry Osipenko <digetx@...il.com>,
        krzysztof.kozlowski@...onical.com, robh+dt@...nel.org,
        thierry.reding@...il.com, jonathanh@...dia.com,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-tegra@...r.kernel.org
Cc:     vdumpa@...dia.com, Snikam@...dia.com
Subject: Re: [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186
 onward



On 3/20/2022 6:23 PM, Dmitry Osipenko wrote:
> External email: Use caution opening links or attachments
> 
> 
> 16.03.2022 12:25, Ashish Mhetre пишет:
>> +static int tegra186_mc_get_channel(const struct tegra_mc *mc, int *mc_channel)
>> +{
>> +     u32 status;
>> +
>> +     status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS);
>> +
>> +     switch (status & mc->soc->int_channel_mask) {
>> +     case BIT(0):
>> +             *mc_channel = 0;
>> +             break;
>> +
>> +     case BIT(1):
>> +             *mc_channel = 1;
>> +             break;
>> +
>> +     case BIT(2):
>> +             *mc_channel = 2;
>> +             break;
>> +
>> +     case BIT(3):
>> +             *mc_channel = 3;
>> +             break;
> 
> This won't work if multiple bits are set at once.

I talked with our HW team and they said that it's technically possible
that interrupts can come at multiple channels at same time. SW can take
care of this by logging interrupts at first channel and then clearing
bit of that. Then take care of interrupts from next channel and so on.
I'll update the patches accordingly in next version.