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Message-ID: <314a9839609898933bf19a6d29b83807391845af.camel@mediatek.com>
Date: Wed, 23 Mar 2022 18:23:15 +0800
From: Rex-BC Chen <rex-bc.chen@...iatek.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>,
"matthias.bgg@...il.com" <matthias.bgg@...il.com>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kernel@...labora.com" <kernel@...labora.com>
Subject: Re: [PATCH v2] soc: mediatek: mmsys: Add sw0_rst_offset for MT8192
On Wed, 2022-03-23 at 17:19 +0800, AngeloGioacchino Del Regno wrote:
> MT8192 has the same sw0 reset offset as MT8186: add the parameter
> to be able to use mmsys as a reset controller for managing at
> least the DSI reset line.
>
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@...labora.com>
> ---
>
> v2: Change the offset to 0x160 (as defined for MT8186). Thanks, Rex-
> BC!
>
You are welcome!
Reviewed-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
> drivers/soc/mediatek/mtk-mmsys.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..f69521fabcce 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -70,6 +70,7 @@ static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> .clk_driver = "clk-mt8192-mm",
> .routes = mmsys_mt8192_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> + .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
> };
>
> static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =
> {
> --
> 2.35.1
>
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