lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <c150e9ed7faa4c06f55f7d7623655b65c8575121.camel@mediatek.com>
Date:   Thu, 24 Mar 2022 17:42:29 +0800
From:   Jia-Wei Chang <jia-wei.chang@...iatek.com>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        "Rafael J . Wysocki" <rafael@...nel.org>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        "Rob Herring" <robh+dt@...nel.org>,
        Liam Girdwood <lgirdwood@...il.com>,
        "Mark Brown" <broonie@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>
CC:     <linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>, <fan.chen@...iatek.com>,
        <louis.yu@...iatek.com>, <roger.lu@...iatek.com>,
        <Allen-yy.Lin@...iatek.com>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        <hsinyi@...gle.com>,
        Jia-Wei Chang <jia-wei.chang@...iatek.corp-partner.google.com>
Subject: Re: [PATCH 2/4] dt-bindings: cpufreq: mediatek: add mt8186 cpufreq
 dt-bindings

On Mon, 2022-03-07 at 19:59 +0100, Krzysztof Kozlowski wrote:
> On 07/03/2022 13:21, Tim Chang wrote:
> > 1. add cci property.
> > 2. add example of MT8186.
> 
> One logical change at a time. Are these related? Why entirely new
> example just for "cci" node? Maybe this should be part of existing
> example?

Yes, the cci property is required in some SoC, e.g. mt8183 and mt8186,
because cpu and cci share the same power supplies.
I will update the commit message and add an example of mt8186 to
present usage of cci.

> 
> > 
> > Signed-off-by: Jia-Wei Chang <
> > jia-wei.chang@...iatek.corp-partner.google.com>
> > ---
> >  .../bindings/cpufreq/cpufreq-mediatek.yaml    | 41
> > +++++++++++++++++++
> >  1 file changed, 41 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > index 584946eb3790..d3ce17fd8fcf 100644
> > --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-
> > mediatek.yaml
> > @@ -48,6 +48,10 @@ properties:
> >        When absent, the voltage scaling flow is handled by
> > hardware, hence no
> >        software "voltage tracking" is needed.
> >  
> > +  cci:
> > +    description:
> > +      Phandle of the cci to be linked with the phandle of CPU if
> > present.
> 
> This does not look like a standard type, so you need type.

Sure, I will add the type for it in the next version.

> 
> 
> 
> Best regards,
> Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ