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Message-ID: <20220324183323.31414-5-alisaidi@amazon.com>
Date: Thu, 24 Mar 2022 18:33:23 +0000
From: Ali Saidi <alisaidi@...zon.com>
To: <linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <german.gomez@....com>,
<leo.yan@...aro.org>, <acme@...nel.org>
CC: <alisaidi@...zon.com>, <benh@...nel.crashing.org>,
<Nick.Forrington@....com>, <alexander.shishkin@...ux.intel.com>,
<andrew.kilroy@....com>, <james.clark@....com>,
<john.garry@...wei.com>, <jolsa@...nel.org>, <kjain@...ux.ibm.com>,
<lihuafei1@...wei.com>, <mark.rutland@....com>,
<mathieu.poirier@...aro.org>, <mingo@...hat.com>,
<namhyung@...nel.org>, <peterz@...radead.org>, <will@...nel.org>
Subject: [PATCH v4 4/4] perf mem: Support HITM for when mem_lvl_num is any
For loads that hit in a the LLC snoop filter and are fulfilled from a
higher level cache on arm64 Neoverse cores, it's not usually clear what
the true level of the cache the data came from (i.e. a transfer from a
core could come from it's L1 or L2). Instead of making an assumption of
where the line came from, add support for incrementing HITM if the
source is CACHE_ANY.
Since other architectures don't seem to populate the mem_lvl_num field
here there shouldn't be a change in functionality.
Signed-off-by: Ali Saidi <alisaidi@...zon.com>
Tested-by: German Gomez <german.gomez@....com>
Reviewed-by: German Gomez <german.gomez@....com>
---
tools/perf/util/mem-events.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
index e5e405185498..084977cfebef 100644
--- a/tools/perf/util/mem-events.c
+++ b/tools/perf/util/mem-events.c
@@ -539,6 +539,15 @@ do { \
stats->ld_llchit++;
}
+ /*
+ * A hit in another cores cache must mean a llc snoop
+ * filter hit
+ */
+ if (lnum == P(LVLNUM, ANY_CACHE)) {
+ if (snoop & P(SNOOP, HITM))
+ HITM_INC(lcl_hitm);
+ }
+
if (lvl & P(LVL, LOC_RAM) || lnum == P(LVLNUM, RAM)) {
stats->lcl_dram++;
if (snoop & P(SNOOP, HIT))
--
2.32.0
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