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Message-ID: <09b8c4d2-6cdd-b41b-4913-f9f2f7f4d7c7@gmail.com>
Date: Fri, 25 Mar 2022 16:47:36 +0100
From: Matthias Brugger <matthias.bgg@...il.com>
To: Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Chun-Kuang Hu <chunkuang.hu@...nel.org>
Cc: Project_Global_Chrome_Upstream_Group@...iatek.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
Chen-Yu Tsai <wenst@...omium.org>,
Ryder Lee <ryder.lee@...nel.org>,
Hui Liu <hui.liu@...iatek.com>
Subject: Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes
On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add display nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a77d405dd508..59183fb6c80b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1205,6 +1205,13 @@
> #clock-cells = <1>;
> };
>
> + mutex: mutex@...01000 {
> + compatible = "mediatek,mt8192-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
We are missing power-domains property.
> + };
> +
> smi_common: smi@...02000 {
> compatible = "mediatek,mt8192-smi-common";
> reg = <0 0x14002000 0 0x1000>;
> @@ -1236,6 +1243,110 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> };
>
> + ovl0: ovl@...05000 {
> + compatible = "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
> + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + };
> +
> + ovl_2l0: ovl@...06000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
> + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
olv and ovl-2l binding mention that the node should be a sibling of mmsys, but
this does not hold anymore, correct? Chun-Kuang can you help to fix the binding
description?
> + };
> +
> + rdma0: rdma@...07000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
> + mediatek,larb = <&larb0>;
> + mediatek,rdma-fifo-size = <5120>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
Same here, bindings says it should be a sibling of mmsys. Apart from that the
maximal rdma-fifo-size isn't specified for all SoCs including mt1892.
> + };
> +
> + color0: color@...09000 {
> + compatible = "mediatek,mt8192-disp-color",
> + "mediatek,mt8173-disp-color";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + };
Same here, binding description needs fixed, please check for other bindings as
well. The node here looks good.
> +
> + ccorr0: ccorr@...0a000 {
> + compatible = "mediatek,mt8192-disp-ccorr";
> + reg = <0 0x1400a000 0 0x1000>;
> + interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + };
> +
> + aal0: aal@...0b000 {
> + compatible = "mediatek,mt8192-disp-aal",
> + "mediatek,mt8193-disp-aal";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + };
> +
> + gamma0: gamma@...0c000 {
> + compatible = "mediatek,mt8192-disp-gamma",
> + "mediatek,mt8183-disp-gamma";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + };
> +
> + postmask0: postmask@...0d000 {
> + compatible = "mediatek,mt8192-disp-postmask";
> + reg = <0 0x1400d000 0 0x1000>;
> + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> + iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
No iommus mentioned in binding description.
Regards,
Matthias
> + };
> +
> + dither0: dither@...0e000 {
> + compatible = "mediatek,mt8192-disp-dither",
> + "mediatek,mt8183-disp-dither";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + };
> +
> + ovl_2l2: ovl@...14000 {
> + compatible = "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> + };
> +
> + rdma4: rdma@...15000 {
> + compatible = "mediatek,mt8192-disp-rdma";
> + reg = <0 0x14015000 0 0x1000>;
> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> + mediatek,rdma-fifo-size = <2048>;
> + };
> +
> dpi0: dpi@...16000 {
> compatible = "mediatek,mt8192-dpi";
> reg = <0 0x14016000 0 0x1000>;
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