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Date: Sat, 26 Mar 2022 10:43:12 -0400
From: Jesse Taube <mr.bossman075@...il.com>
To: linux-imx@....com
Cc: robh+dt@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
festevam@...il.com, aisheng.dong@....com, stefan@...er.ch,
linus.walleij@...aro.org, daniel.lezcano@...aro.org,
tglx@...utronix.de, arnd@...db.de, olof@...om.net, soc@...nel.org,
linux@...linux.org.uk, abel.vesa@....com, dev@...xeye.de,
marcel.ziswiler@...adex.com, tharvey@...eworks.com,
leoyang.li@....com, sebastian.reichel@...labora.com,
cniedermaier@...electronics.com, Mr.Bossman075@...il.com,
clin@...e.com, giulio.benetti@...ettiengineering.com,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-gpio@...r.kernel.org
Subject: [PATCH v1 11/12] ARM: dts: imx: Add i.MXRT1170-EVK support
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and M4 core.
The EVK provides 64 MB SDRAM, 128 MB Quad SPI flash, Micro SD card socket,
two USB 2.0 OTG, and two Ethernet ports.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
Cc: Giulio Benetti <giulio.benetti@...ettiengineering.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@...il.com>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imxrt1170-evk.dts | 126 +++++++++++++
arch/arm/boot/dts/imxrt1170.dtsi | 278 ++++++++++++++++++++++++++++
3 files changed, 406 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/boot/dts/imxrt1170.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 07acd6189cae..87ae30818f39 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -724,7 +724,8 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_IMXRT) += \
- imxrt1050-evk.dtb
+ imxrt1050-evk.dtb \
+ imxrt1170-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imxrt1170-evk.dts b/arch/arm/boot/dts/imxrt1170-evk.dts
new file mode 100644
index 000000000000..fc3b41de8215
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1170-evk.dts
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <Mr.Bossman075@...il.com>
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+ model = "NXP imxrt1170-evk board";
+ compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ gpio7 = &gpio8;
+ gpio8 = &gpio9;
+ gpio9 = &gpio10;
+ gpio10 = &gpio11;
+ gpio11 = &gpio12;
+ gpio12 = &gpio13;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ usbphy0 = &usbphy1;
+ };
+
+ memory@...40000 {
+ device_type = "memory";
+ reg = <0x20240000 0xf0000>;
+ };
+
+ memory@...00000 {
+ device_type = "memory";
+ reg = <0x80000000 0x4000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio9 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <
+ IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1
+ IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1
+ >;
+ };
+
+ pinctrl_pwm0: pwm0grp {
+ fsl,pins = <
+ IOMUXC_GPIO_AD_11_USB_OTG1_OC 0xf1
+ >;
+ };
+
+ pinctrl_usbotg1_id: pinctrl_usbotg1_id {
+ fsl,pins = <
+ IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0xf1
+ >;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <
+ IOMUXC_GPIO_AD_32_USDHC1_CD_B
+ 0x1B000
+ IOMUXC_GPIO_AD_34_USDHC1_VSELECT
+ 0xB069
+ IOMUXC_GPIO_SD_B1_00_USDHC1_CMD
+ 0x17061
+ IOMUXC_GPIO_SD_B1_01_USDHC1_CLK
+ 0x17061
+ IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3
+ 0x17061
+ IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2
+ 0x17061
+ IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1
+ 0x17061
+ IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0
+ 0x17061
+ >;
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ status = "okay";
+ broken-cd;
+};
diff --git a/arch/arm/boot/dts/imxrt1170.dtsi b/arch/arm/boot/dts/imxrt1170.dtsi
new file mode 100644
index 000000000000..fb53347571a9
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1170.dtsi
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <Mr.Bossman075@...il.com>
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1170-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x40000>;
+ no-map;
+ linux,dma-default;
+ };
+ };
+
+ clocks {
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ rcosc16M: rcosc16M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ };
+
+ osc32k: osc32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ osc3M: osc3M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3000000>;
+ };
+ };
+
+ soc {
+ anatop: anatop@...84000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x40c84000 0x4000>;
+ };
+
+ clks: ccm@...c0000 {
+ compatible = "fsl,imxrt1170-ccm";
+ reg = <0x40cc0000 0x4000>;
+ clocks = <&osc>, <&rcosc16M>, <&osc32k>;
+ clock-names = "osc", "rcosc16M", "osc32k";
+ #clock-cells = <1>;
+ };
+
+ edma1: dma-controller@...70000 {
+ #dma-cells = <2>;
+ compatible = "fsl,imx7ulp-edma";
+ reg = <0x40070000 0x4000>,
+ <0x40074000 0x4000>;
+ dma-channels = <32>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
+ clock-names = "dma", "dmamux0";
+ clocks = <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_M4>;
+ };
+
+ gpio1: gpio@...2c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x4012c000 0x4000>;
+ interrupts = <100>, <101>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@...30000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40130000 0x4000>;
+ interrupts = <102>, <103>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@...34000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40134000 0x4000>;
+ interrupts = <104>, <105>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@...38000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40138000 0x4000>;
+ interrupts = <106>, <107>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@...3c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x4013c000 0x4000>;
+ interrupts = <108>, <109>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@...40000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40140000 0x4000>;
+ interrupts = <61>, <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio@...5c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c5c000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio8: gpio@...60000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c60000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio9: gpio@...64000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c64000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio10: gpio@...68000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c68000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio11: gpio@...6c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c6c000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio12: gpio@...70000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c70000 0x4000>;
+ interrupts = <61>, <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio13: gpio@...a0000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40ca0000 0x4000>;
+ interrupts = <93>, <93>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpt: timer@...ec000 {
+ compatible = "fsl,imxrt1170-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
+ reg = <0x400ec000 0x4000>;
+ interrupts = <119>;
+ clocks = <&osc3M>;
+ clock-names = "per";
+ };
+
+ iomuxc: iomuxc@...e8000 {
+ compatible = "fsl,imxrt1170-iomuxc";
+ reg = <0x400e8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ lpuart1: serial@...7c000 {
+ compatible = "fsl,imxrt1170-lpuart", "fsl,imxrt1050-lpuart", "fsl,imx7ulp-lpuart";
+ reg = <0x4007c000 0x4000>;
+ interrupts = <20>;
+ clocks = <&clks IMXRT1170_CLK_LPUART1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ usdhc1: mmc@...18000 {
+ compatible ="fsl,imxrt1050-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x40418000 0x10000>;
+ interrupts = <133>;
+ clocks = <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,wp-controller;
+ no-1-8-v;
+ max-frequency = <4000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+
+ usbmisc1: usbmisc@...30200 {
+ compatible = "fsl,imx7ulp-usbmisc";
+ #index-cells = <1>;
+ reg = <0x40430200 0x200>;
+ };
+
+ usbotg1: usb@...30000 {
+ compatible = "fsl,imx7ulp-usb";
+ reg = <0x40430000 0x200>;
+ interrupts = <136>;
+ clocks = <&clks IMXRT1170_CLK_USB>;
+ phys = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbphy1: usb-phy@...34000 {
+ compatible = "fsl,imx7ulp-usbphy";
+ reg = <0x40434000 0x1000>;
+ interrupts = <90>;
+ clocks = <&clks IMXRT1170_CLK_USB>;
+ #phy-cells = <0>;
+ };
+
+ };
+};
--
2.34.1
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