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Message-ID: <DM6PR04MB657599A82C0513C46B80EB47FC1C9@DM6PR04MB6575.namprd04.prod.outlook.com>
Date: Sun, 27 Mar 2022 08:09:38 +0000
From: Avri Altman <Avri.Altman@....com>
To: Adrian Hunter <adrian.hunter@...el.com>,
Christian Löhle <CLoehle@...erstone.com>,
Michael Wu <michael@...winnertech.com>,
"ulf.hansson@...aro.org" <ulf.hansson@...aro.org>,
"beanhuo@...ron.com" <beanhuo@...ron.com>,
"porzio@...il.com" <porzio@...il.com>
CC: "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
allwinner-opensource-support
<allwinner-opensource-support@...winnertech.com>
Subject: RE: [PATCH] mmc: block: enable cache-flushing when mmc cache is on
> On 16.3.2022 16.46, Christian Löhle wrote:
> >> So we are not going to let the block layer know about SD cache?
> >> Or is it a separate change?
> >
> > I have some code for this laying around, but as it requires reading,
> > parsing and writing Function Registers, in particular PEH, it's a lot of
> boilerplate code to get the functionality, but I'll clean it up and send a patch
> in the coming weeks.
> >
>
> We have the sd cache flush. We would presumably just need to call
> blk_queue_write_cache() for the !mmc_card_mmc(card) case e.g.
>
> if (mmc_has_reliable_write(card)) {
> md->flags |= MMC_BLK_REL_WR;
> enable_fua = true;
> }
>
> if (mmc_cache_enabled(card->host))
> enable_cache = true;
>
> blk_queue_write_cache(md->queue.queue, enable_cache, enable_fua);
>
> Avri, were you objecting to that?
Hi, Sorry for my late response.
Yes - That's fine.
Thanks,
Avri
>
> >
> >
> >
> >
> > From: Adrian Hunter <adrian.hunter@...el.com>
> > Sent: Wednesday, March 16, 2022 12:28 PM
> > To: Avri Altman; Michael Wu; ulf.hansson@...aro.org;
> > beanhuo@...ron.com; porzio@...il.com
> > Cc: linux-mmc@...r.kernel.org; linux-kernel@...r.kernel.org;
> > allwinner-opensource-support
> > Subject: Re: [PATCH] mmc: block: enable cache-flushing when mmc cache
> > is on
> >
> > On 16.3.2022 13.09, Avri Altman wrote:
> >>> Hi Avril & Adrian,
> >>> Thanks for your efforts. Could we have an agreement now --
> >>>
> >>> 1. enabling-cache and cmd23/reliable-write should be independent;
> >>>
> >>> Here's what I found in the spec JESD84-B51:
> >>> > 6.6.31 Cache
> >>> > Caching of data shall apply only for the single block
> >>> > read/write(CMD17/24), pre-defined multiple block
> >>> > read/write(CMD23+CMD18/25) and open ended multiple block
> >>> > read/write(CMD18/25+CMD12) commands and excludes any other
> access
> >>> > e.g., to the register space(e.g., CMD6).
> >>> Which means with CMD18/25+CMD12 (without using CMD23), the cache
> can
> >>> also be enabled. Maybe this could be an evidence of the independence
> >>> between enabling-cache and cmd23/reliable-write?
> >> Acked-by: Avri Altman <avri.altman@....com>
> >>
> >> Thanks,
> >> Avri
> >>
> >>>
> >>> 2. We don't consider supporting SD in this change.
> >>>
> >>> > On 14/03/2022 19:10, Avri Altman wrote:
> >>> >> Here is what our SD system guys wrote:
> >>> >> " In SD we don’t support reliable write and this eMMC driver may not
> >>> >> be utilizing the cache feature we added in SD5.0.
> >>> >> The method of cache flush is different between SD and eMMC."
> >>> >>
> >>> >> So adding SD seems to be out of scope of this change.
> >>>
> >>> Is there anything else I can do about this patch? Thanks again.
> >
> > So we are not going to let the block layer know about SD cache?
> > Or is it a separate change?
> > =
> > Hyperstone GmbH | Reichenaustr. 39a | 78467 Konstanz Managing
> > Director: Dr. Jan Peter Berns.
> > Commercial register of local courts: Freiburg HRB381782
> >
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