lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <YkHX3/8BbXo4obWI@sirena.org.uk>
Date:   Mon, 28 Mar 2022 16:44:31 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Sameer Pujar <spujar@...dia.com>
Cc:     robh+dt@...nel.org, krzk+dt@...nel.org, thierry.reding@...il.com,
        lgirdwood@...il.com, perex@...ex.cz, tiwai@...e.com,
        jonathanh@...dia.com, catalin.marinas@....com, will@...nel.org,
        alsa-devel@...a-project.org, devicetree@...r.kernel.org,
        linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 2/6] ASoC: tegra: Add Tegra186 based ASRC driver

On Mon, Mar 28, 2022 at 11:35:22AM +0530, Sameer Pujar wrote:

> +	regcache_cache_only(asrc->regmap, false);
> +	regcache_sync(asrc->regmap);
> +
> +	/* Setup global registers */
> +	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SOFT_RESET, 0x1);
> +	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR,
> +		     TEGRA186_ASRC_ARAM_START_ADDR);
> +	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_INT_MASK, 0x01);
> +	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB,
> +		     TEGRA186_ASRC_GLOBAL_EN);
> +	regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_INT_CLEAR, 0x01);

This seems weird - we resync the cache, then do a soft reset (which
presumably desyncs the cache) and then explicitly restore a bunch of
things (hopefully everything that was in the cached state?).  This is
certainly very much not idiomatic and looks worrying.  Are you sure that
the device is getting anything out of the register cache?

> +static int tegra186_asrc_put_ratio_source(struct snd_kcontrol *kcontrol,
> +					  struct snd_ctl_elem_value *ucontrol)
> +{
> +	struct soc_enum *asrc_private =
> +		(struct soc_enum  *)kcontrol->private_value;
> +	struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
> +	struct tegra186_asrc *asrc = snd_soc_component_get_drvdata(cmpnt);
> +	unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE;
> +
> +	asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0];
> +
> +	regmap_update_bits(asrc->regmap, asrc_private->reg,
> +			   TEGRA186_ASRC_STREAM_RATIO_TYPE_MASK,
> +			   asrc->lane[id].ratio_source);
> +
> +	return 1;
> +}

This should only return 1 if the value actually changed, you can use
regmap_update_bits_check() to detect the change.  Current mixer-test
ought to spot this.

> +static const struct snd_kcontrol_new tegra186_asrc_controls[] = {
> +	/* Controls for integer part of ratio */
> +	SOC_SINGLE_EXT("Ratio1 Integer Part",
> +		       ASRC_STREAM_REG(TEGRA186_ASRC_RATIO_INT_PART, 0),
> +		       0, TEGRA186_ASRC_STREAM_RATIO_INT_PART_MASK, 0,
> +		       tegra186_asrc_get_ratio_int,
> +		       tegra186_asrc_put_ratio_int),

Can't the driver work out the ratios based on...

> +	/* Source of ratio provider */
> +	SOC_ENUM_EXT("Ratio1 Source", src_select1,
> +		     tegra186_asrc_get_ratio_source,
> +		     tegra186_asrc_put_ratio_source),

...the sources?  Or does it need to be configured before either side is
ready in which case this might be the best we can do for now.

Download attachment "signature.asc" of type "application/pgp-signature" (489 bytes)

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ