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Message-ID: <51f8baea-6562-1d6b-c409-9c362f0b2fc5@gmail.com>
Date: Mon, 28 Mar 2022 13:10:45 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: Allen-KH Cheng <allen-kh.cheng@...iatek.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Cc: Project_Global_Chrome_Upstream_Group@...iatek.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-mediatek@...ts.infradead.org,
Chen-Yu Tsai <wenst@...omium.org>,
Ryder Lee <ryder.lee@...nel.org>,
Hui Liu <hui.liu@...iatek.com>
Subject: Re: [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node
On 18/03/2022 15:45, Allen-KH Cheng wrote:
> Add pwm node for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index f0f0f067c023..ea98b2230f18 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -625,6 +625,17 @@
> status = "disabled";
> };
>
> + pwm0: pwm@...0e000 {
> + compatible = "mediatek,mt8183-disp-pwm";
> + reg = <0 0x1100e000 0 0x1000>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>;
Binding description is missing interrupt property. Remeber that the DT should
describe the HW, so we need to update the binding description.
I just wonder what the IRQ signals, as it is not used by the driver. Definitely
a good candidate to make the commit message more sound. So please add it there.
Thanks!
Matthias
> + #pwm-cells = <2>;
> + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> + <&infracfg CLK_INFRA_DISP_PWM>;
> + clock-names = "main", "mm";
> + status = "disabled";
> + };
> +
> spi1: spi@...10000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
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