linux-kernel - Re: [PATCH 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20220329052049epcms2p623bd47de38aba8a43689e515bc712ede@epcms2p6>
Date:   Tue, 29 Mar 2022 14:20:49 +0900
From:   이왕석 <wangseok.lee@...sung.com>
To:     Rob Herring <robh@...nel.org>
CC:     "kernel@...s.com" <kernel@...s.com>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
        "kw@...ux.com" <kw@...ux.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        전문기 <moonki.jun@...sung.com>,
        "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "linux-arm-kernel@...s.com" <linux-arm-kernel@...s.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "jesper.nilsson@...s.com" <jesper.nilsson@...s.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kishon@...com" <kishon@...com>,
        "lars.persson@...s.com" <lars.persson@...s.com>
Subject: Re: [PATCH 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy

> --------- Original Message ---------
> Sender : Rob Herring <robh@...nel.org>
> Date : 2022-03-28 21:51 (GMT+9)
> Title : Re: [PATCH 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy
> 
> On Mon, 28 Mar 2022 17:43:19 +0900, �댁���� wrote:
>> Add description to support Axis, ARTPEC-8 SoC.
>> ARTPEC-8 is the SoC platform of Axis Communications
>> and PCIe phy is designed based on SAMSUNG PHY.
>> 
>> Signed-off-by: Wangseok Lee <wangseok.lee@...sung.com>
>> ---
>>  .../bindings/phy/axis,artpec8-pcie-phy.yaml        | 67 ++++++++++++++++++++++
>>  1 file changed, 67 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
>> 
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.example.dt.yaml:0:0: /example-0/artec8/pcie-phy@...80000: failed to match any schema with compatible: ['samsung,artpec8-pcie-phy']
> 
> doc reference errors (make refcheckdocs):
> 
> See https://protect2.fireeye.com/v1/url?k=0fdd5edc-6f3fc381-0fdcd593-000babd9f1ba-cd731013fdd72389&q=1&e=df20f229-606a-4e6a-bcb2-2cbdc399248e&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F1610068
> 
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit.

Hello Rob Herring
Thanks for your review.

I wrote the wrong "compatible" value.
so i will modify this part and summit it again.
also i checked the result by performing 
"make dt_binding_check DT_SCHEMA_FILES=
Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml".

Thanks.