linux-kernel - Re: [PATCH v3, 03/10] dt-bindings: media: mtk-vcodec: Adds encoder cores dt-bindings for mt8195

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YkMFGbgYq5DhLjt8@robh.at.kernel.org>
Date:   Tue, 29 Mar 2022 08:09:45 -0500
From:   Rob Herring <robh@...nel.org>
To:     Irui Wang <irui.wang@...iatek.com>
Cc:     Hans Verkuil <hverkuil-cisco@...all.nl>,
        Tzung-Bi Shih <tzungbi@...omium.org>,
        Alexandre Courbot <acourbot@...omium.org>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Tomasz Figa <tfiga@...gle.com>,
        angelogioacchino.delregno@...labora.com,
        Yong Wu <yong.wu@...iatek.com>,
        Tiffany Lin <tiffany.lin@...iatek.com>,
        Andrew-CT Chen <andrew-ct.chen@...iatek.com>,
        Hsin-Yi Wang <hsinyi@...omium.org>,
        Maoguang Meng <maoguang.meng@...iatek.com>,
        Longfei Wang <longfei.wang@...iatek.com>,
        Yunfei Dong <yunfei.dong@...iatek.com>,
        Fritz Koenig <frkoenig@...omium.org>,
        linux-media@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        srv_heupstream@...iatek.com, linux-mediatek@...ts.infradead.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v3, 03/10] dt-bindings: media: mtk-vcodec: Adds encoder
 cores dt-bindings for mt8195

On Tue, Mar 29, 2022 at 09:26:37AM +0800, Irui Wang wrote:
> Dear Rob,
> 
> Many thanks for your attention.
> 
> On Mon, 2022-03-28 at 08:48 -0500, Rob Herring wrote:
> > On Sat, Mar 26, 2022 at 10:00:55AM +0800, Irui Wang wrote:
> > > Dear Rob,
> > > 
> > > Thanks for your review and comments.
> > > 
> > > On Fri, 2022-03-25 at 15:57 -0500, Rob Herring wrote:
> > > > On Thu, Mar 17, 2022 at 04:22:23PM +0800, Irui Wang wrote:
> > > > > Adds encoder cores dt-bindings for mt8195.

[...]

> > > > > +      mediatek,core-id:
> > > > > +        $ref: /schemas/types.yaml#/definitions/uint32
> > > > > +        description: |
> > > > > +          Current encoder core id.
> > > > 
> > > > What is this for and what does its value correspond to in the
> > > > h/w.
> > > > We 
> > > > generally don't do made up indices in DT.
> > > 
> > > It's for encoder core id, core@...20000 must be core-0, 
> > > core@...20000
> > > must be core-1, we add this property in each child node, so we can 
> > > get core-id in drivers. If it can't ref "uint32" types yaml, would 
> > > you mind giving some more suggestions ?
> > 
> > I still don't understand why it is needed. What is 'core-0'?
> > 
> > Is there some functional difference between the cores? If so,
> > describe 
> > that difference.
> > 
> > Rob
> 
> They are two different pieces of hardware, it's our encoder hardware
> design. There are two encoder hardware cores inside MT8195, named core0
> and core1(we can rename it, but core id should be declared),
> for core0, its module base address is 0x1A02_0000, uses IOMMU
> "vdo0_iommu" and power domain "POWER_DOMAIN_VENC",
> for core1, its module base address is 0x1B02_0000, uses IOMMU
> "vpp_iommu" and power domain "POWER_DOMAIN_VENC_CORE1".
> So the two encoder cores have their own base, IRQ, clock, power, etc.
> Each core can encode independently, moreover, they can work together
> for higher performance. 
> We will describe more details in YAML about it if it's OK for you.

All the resources you list are in the child nodes, so you don't need 0 
and 1 numbering for those. 

Looking at the driver patches, the only thing I see distinguishing 
core numbers is this:

"frame#0 uses core#0, frame#1 uses core#1, frame#2 uses core#0...,

Lock the device and enable the clock by used core, for sequence
header encoding, it always uses core#0."

Is this a requirement in the h/w or just what the driver picked? IOW, 
could frame#0 use core#1?

Rob