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Message-ID: <1648656179-10347-5-git-send-email-quic_sbillaka@quicinc.com>
Date: Wed, 30 Mar 2022 21:32:55 +0530
From: Sankeerth Billakanti <quic_sbillaka@...cinc.com>
To: <dri-devel@...ts.freedesktop.org>, <linux-arm-msm@...r.kernel.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>
CC: Sankeerth Billakanti <quic_sbillaka@...cinc.com>,
<robdclark@...il.com>, <seanpaul@...omium.org>,
<swboyd@...omium.org>, <quic_kalyant@...cinc.com>,
<quic_abhinavk@...cinc.com>, <dianders@...omium.org>,
<quic_khsieh@...cinc.com>, <bjorn.andersson@...aro.org>,
<sean@...rly.run>, <airlied@...ux.ie>, <daniel@...ll.ch>,
<dmitry.baryshkov@...aro.org>, <quic_vproddut@...cinc.com>,
<quic_aravindh@...cinc.com>
Subject: [PATCH v6 4/8] drm/msm/dp: avoid handling masked interrupts
The interrupt register will still reflect the connect and disconnect
interrupt status without generating an actual HW interrupt.
The controller driver should not handle those masked interrupts.
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@...cinc.com>
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 3c16f95..1809ce2 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -608,13 +608,14 @@ u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- int isr = 0;
+ int isr, mask;
isr = dp_read_aux(catalog, REG_DP_DP_HPD_INT_STATUS);
dp_write_aux(catalog, REG_DP_DP_HPD_INT_ACK,
(isr & DP_DP_HPD_INT_MASK));
+ mask = dp_read_aux(catalog, REG_DP_DP_HPD_INT_MASK);
- return isr;
+ return isr & (DP_DP_HPD_STATE_STATUS_MASK | mask);
}
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
--
2.7.4
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